shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 10:58:48 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: px30: Export clk id for sclk_i2s0_tx/rx mux

Browse Source 
Change-Id: I697d20fb0c69f9dcd76aaf2d18d666db2241360d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Sugar Zhang
2018-12-04 15:05:41 +08:00
committed by Tao Huang
parent 03fb4f4b0f
commit 2b1b3a5b70
2 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/rockchip/clk-px30.c
View File

@@ -212,11 +212,11 @@ static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
MUX(SCLK_I2S0_TX_MUX, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
MUX(SCLK_I2S0_RX_MUX, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =

2
include/dt-bindings/clock/px30-cru.h
View File

@@ -87,6 +87,8 @@
#define SCLK_UART1_SRC 85
#define SCLK_SDMMC_DIV 86
#define SCLK_SDMMC_DIV50 87
#define SCLK_I2S0_TX_MUX 88
#define SCLK_I2S0_RX_MUX 89
/* dclk gates */
#define DCLK_VOPB 150