shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 18:41:58 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: drv: add mode crtc_* timing covert

Browse Source 
The mode contains two copies of timings, first are the plain and
origin timings, this should keep unchanged, the second are copy
from the first timing by add some computed and special fixup, this
is associate with hardware.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ib841af1bbdc970d205d8aec3f83c6238a13bdede
This commit is contained in:
Sandy Huang
2024-04-10 20:02:24 +08:00
committed by Tao Huang
parent 3e568d5f2f
commit 2b31b121d9
1 changed files with 23 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@@ -176,11 +176,22 @@ void drm_mode_convert_to_split_mode(struct drm_display_mode *mode)
hbp = mode->htotal - mode->hsync_end;
mode->clock *= 2;
mode->crtc_clock *= 2;
mode->hdisplay = hactive * 2;
mode->hsync_start = mode->hdisplay + hfp * 2;
mode->hsync_end = mode->hsync_start + hsync * 2;
mode->htotal = mode->hsync_end + hbp * 2;
hactive = mode->crtc_hdisplay;
hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;
hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
hbp = mode->crtc_htotal - mode->crtc_hsync_end;
mode->crtc_clock *= 2;
mode->crtc_hdisplay = hactive * 2;
mode->crtc_hsync_start = mode->crtc_hdisplay + hfp * 2;
mode->crtc_hsync_end = mode->crtc_hsync_start + hsync * 2;
mode->crtc_htotal = mode->crtc_hsync_end + hbp * 2;
drm_mode_set_name(mode);
}
EXPORT_SYMBOL(drm_mode_convert_to_split_mode);
@@ -195,11 +206,21 @@ void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode)
hbp = mode->htotal - mode->hsync_end;
mode->clock /= 2;
mode->crtc_clock /= 2;
mode->hdisplay = hactive / 2;
mode->hsync_start = mode->hdisplay + hfp / 2;
mode->hsync_end = mode->hsync_start + hsync / 2;
mode->htotal = mode->hsync_end + hbp / 2;
hactive = mode->crtc_hdisplay;
hfp = mode->crtc_hsync_start - mode->crtc_hdisplay;
hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
hbp = mode->crtc_htotal - mode->crtc_hsync_end;
mode->crtc_clock /= 2;
mode->crtc_hdisplay = hactive / 2;
mode->crtc_hsync_start = mode->crtc_hdisplay + hfp / 2;
mode->crtc_hsync_end = mode->crtc_hsync_start + hsync / 2;
mode->crtc_htotal = mode->crtc_hsync_end + hbp / 2;
}
EXPORT_SYMBOL(drm_mode_convert_to_origin_mode);