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mmc: dw_mmc-rockchip: Add memory clock auto-gating support

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Per design recommendation, memory clock could be gate if no transfer is
on-flight which could help save power. This feature is introduced along
with internal phase support. This patch enables the feature.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I36b90a17742da63f229e61167277bbbdc676695b
This commit is contained in:
Shawn Lin
2025-02-14 08:38:39 +08:00
committed by Tao Huang
parent fb7c7cd51d
commit 2c48d055bc
1 changed files with 3 additions and 0 deletions
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3
drivers/mmc/host/dw_mmc-rockchip.c
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@@ -20,6 +20,8 @@
#define USRID_INTER_PHASE 0x20230001
#define SDMMC_TIMING_CON0 0x130
#define SDMMC_TIMING_CON1 0x134
#define SDMMC_MISC_CON 0x138
#define MEM_CLK_AUTOGATE_ENABLE BIT(5)
#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
#define ROCKCHIP_MMC_DEGREE_MASK 0x3
#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
@@ -573,6 +575,7 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
if (priv->usrid == USRID_INTER_PHASE) {
priv->sample_clk = NULL;
priv->drv_clk = NULL;
mci_writel(host, MISC_CON, MEM_CLK_AUTOGATE_ENABLE);
}
host->need_xfer_timer = true;