mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-07 11:26:02 +09:00
Merge commit '36e981880962e2f7580e42a9ea125a6a04c218ad'
* commit '36e981880962e2f7580e42a9ea125a6a04c218ad': Revert "arm64: dts: rockchip: add xhci trb ent quirk for rockchip SoCs" ARM: dts: rockchip: rv1126: Remove unused quirk for usb PCI: rockchip: dw: Remove useless apis PCI: rockchip: dw: Fix resize bar capability for EP arm64: configs: add rockchip_linux_pcie_ep.config for some case use PCIe EP Card arm64: dts: rockchip: add PCIe EP Board for rk3568 media: rockchip: isp: version v2.4.0 media: i2c: techpoint: add tp9951 driver media: i2c: sc3338 adapt sleep_wakeup Change-Id: I88f3b8c3875243e9f302b5f173bb7ce1544e9ccf
This commit is contained in:
Tao Huang
@@ -2569,7 +2569,6 @@
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snps,dis-del-phy-power-chg-quirk;
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snps,tx-ipgap-linecheck-dis-quirk;
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snps,tx-fifo-resize;
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snps,xhci-trb-ent-quirk;
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snps,usb2-lpm-disable;
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snps,parkmode-disable-hs-quirk;
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status = "disabled";
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@@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-pcie-ep-lp4x-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb
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@@ -385,7 +385,6 @@
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snps,dis_u3_susphy_quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,tx-ipgap-linecheck-dis-quirk;
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snps,xhci-trb-ent-quirk;
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snps,parkmode-disable-hs-quirk;
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snps,parkmode-disable-ss-quirk;
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status = "disabled";
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@@ -156,7 +156,6 @@
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snps,dis_u3_susphy_quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,tx-ipgap-linecheck-dis-quirk;
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snps,xhci-trb-ent-quirk;
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status = "disabled";
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};
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};
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641
arch/arm64/boot/dts/rockchip/rk3568-pcie-ep-lp4x-v10-linux.dts
Normal file
641
arch/arm64/boot/dts/rockchip/rk3568-pcie-ep-lp4x-v10-linux.dts
Normal file
@@ -0,0 +1,641 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/rk-input.h>
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#include "rk3568.dtsi"
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/ {
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model = "Rockchip RK3568 PCIe EP LP4X V10 Board";
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compatible = "rockchip,rk3568-pcie-ep-lp4x-v10", "rockchip,rk3568";
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adc_keys: adc-keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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poll-interval = <100>;
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vol-up-key {
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label = "volume up";
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linux,code = <KEY_VOLUMEUP>;
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press-threshold-microvolt = <1750>;
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};
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};
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chosen: chosen {
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bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait default_hugepagesz=32M hugepagesz=32M hugepages=1";
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};
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dc_12v: dc-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <1>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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hdmi_sound: hdmi-sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,mclk-fs = <128>;
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simple-audio-card,name = "rockchip,hdmi";
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status = "disabled";
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||||
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||||
simple-audio-card,cpu {
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sound-dai = <&i2s0_8ch>;
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||||
};
|
||||
simple-audio-card,codec {
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||||
sound-dai = <&hdmi>;
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||||
};
|
||||
};
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||||
|
||||
leds: leds {
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||||
compatible = "gpio-leds";
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||||
|
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work_led: work {
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||||
gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
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||||
|
||||
reserved-memory {
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||||
#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bar0_region: bar0-region@0x3c000000 {
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reg = <0x0 0x3c000000 0x0 0x00400000>;
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};
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bar2_region: bar2-region@0x40000000 {
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||||
reg = <0x0 0x40000000 0x0 0x04000000>;
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||||
};
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||||
};
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||||
test-power {
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status = "okay";
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};
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||||
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||||
vcc3v3_pcie: gpio-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <5000>;
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||||
vin-supply = <&dc_12v>;
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};
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||||
vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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||||
regulator-max-microvolt = <5000000>;
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||||
vin-supply = <&dc_12v>;
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||||
};
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||||
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||||
vcc5v0_host: vcc5v0-host-regulator {
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compatible = "regulator-fixed";
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||||
regulator-name = "vcc5v0_host";
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||||
regulator-boot-on;
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||||
regulator-always-on;
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||||
regulator-min-microvolt = <5000000>;
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||||
regulator-max-microvolt = <5000000>;
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||||
enable-active-high;
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gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_sys>;
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||||
pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_host_en>;
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};
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||||
vcc5v0_otg: vcc5v0-otg-regulator {
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||||
compatible = "regulator-fixed";
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regulator-name = "vcc5v0_otg";
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regulator-min-microvolt = <5000000>;
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||||
regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_sys>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_otg_en>;
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};
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vcc3v3_sys: vcc3v3-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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||||
regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&dc_12v>;
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};
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vccio_1v8: vccio-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "vccio_1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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||||
vin-supply = <&vcc3v3_sys>;
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};
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vccio_3v3: vccio-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vccio_3v3";
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regulator-always-on;
|
||||
regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
|
||||
};
|
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vdd_gpu: vdd-gpu {
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compatible = "pwm-regulator";
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pwms = <&pwm0 0 5000 1>;
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regulator-name = "vdd_gpu";
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regulator-min-microvolt = <810000>;
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regulator-max-microvolt = <1100000>;
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regulator-init-microvolt = <920000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc3v3_sys>;
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status = "okay";
|
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};
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vdd_logic: vdd-logic {
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compatible = "pwm-regulator";
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pwms = <&pwm1 0 5000 1>;
|
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regulator-name = "vdd_logic";
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regulator-min-microvolt = <810000>;
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regulator-max-microvolt = <1000000>;
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regulator-init-microvolt = <920000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc3v3_sys>;
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status = "okay";
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};
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vdd_npu: vdd-npu {
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compatible = "pwm-regulator";
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pwms = <&pwm2 0 5000 1>;
|
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regulator-name = "vdd_npu";
|
||||
regulator-min-microvolt = <810000>;
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regulator-max-microvolt = <1100000>;
|
||||
regulator-init-microvolt = <920000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
pwm-supply = <&vcc3v3_sys>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&bus_npu {
|
||||
bus-supply = <&vdd_logic>;
|
||||
pvtm-supply = <&vdd_cpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
assigned-clocks = <&cru CLK_CAN0>;
|
||||
assigned-clock-rates = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy0_us {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1_usq {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psq {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&dfi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dmc {
|
||||
center-supply = <&vdd_logic>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
rockchip,phy-table =
|
||||
<92812500 0x8009 0x0000 0x0270>,
|
||||
<165000000 0x800b 0x0000 0x026d>,
|
||||
<185625000 0x800b 0x0000 0x01ed>,
|
||||
<297000000 0x800b 0x0000 0x01ad>,
|
||||
<594000000 0x8029 0x0000 0x0088>,
|
||||
<000000000 0x0000 0x0000 0x0000>;
|
||||
};
|
||||
|
||||
&hdmi_in_vp0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
vdd_cpu: rk8600@40 {
|
||||
compatible = "rockchip,rk8600";
|
||||
reg = <0x40>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
regulator-compatible = "rk860x-reg";
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
rockchip,suspend-voltage-selector = <1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2m1_xfer>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3m1_xfer>;
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iep {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iep_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&jpegd {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&jpegd_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mpp_srv {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
compatible = "rockchip,rk3568-pcie-std-ep";
|
||||
memory-region = <&bar0_region>, <&bar2_region>;
|
||||
memory-region-names = "bar0", "bar2";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
status = "okay";
|
||||
pmuio2-supply = <&vccio_3v3>;
|
||||
vccio1-supply = <&vccio_3v3>;
|
||||
vccio3-supply = <&vccio_3v3>;
|
||||
vccio4-supply = <&vccio_3v3>;
|
||||
vccio5-supply = <&vccio_3v3>;
|
||||
vccio6-supply = <&vccio_3v3>;
|
||||
vccio7-supply = <&vccio_3v3>;
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rk_rga {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvdec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvdec_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvenc {
|
||||
venc-supply = <&vdd_logic>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkvenc_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rknpu {
|
||||
rknpu-supply = <&vdd_npu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rknpu_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&vccio_1v8>;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
max-frequency = <150000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vccio_3v3>;
|
||||
vqmmc-supply = <&vccio_3v3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
max-frequency = <150000000>;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
//mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sfc {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "high_speed";
|
||||
pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>;
|
||||
pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>;
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "high_speed";
|
||||
pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>;
|
||||
pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>;
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m1_xfer>;
|
||||
};
|
||||
|
||||
/* RS485 */
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>;
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
vbus-supply = <&vcc5v0_otg>;
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
dr_mode = "otg";
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbhost_dwc3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbhost30 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vdpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vdpu_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vepu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vepu_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
7
arch/arm64/configs/rockchip_linux_pcie_ep.config
Normal file
7
arch/arm64/configs/rockchip_linux_pcie_ep.config
Normal file
@@ -0,0 +1,7 @@
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP_EP=y
|
||||
CONFIG_PCIE_FUNC_RKEP=y
|
||||
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
|
||||
# CONFIG_CGROUP_HUGETLB is not set
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
# CONFIG_PCIE_FUNC_RKEP_USERPAGES is not set
|
||||
@@ -27,6 +27,7 @@
|
||||
#include <media/v4l2-subdev.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include "../platform/rockchip/isp/rkisp_tb_helper.h"
|
||||
#include "cam-sleep-wakeup.h"
|
||||
|
||||
#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
|
||||
|
||||
@@ -158,6 +159,7 @@ struct sc3338 {
|
||||
bool is_thunderboot;
|
||||
bool is_first_streamoff;
|
||||
struct preisp_hdrae_exp_s init_hdrae_exp;
|
||||
struct cam_sw_info *cam_sw_inf;
|
||||
};
|
||||
|
||||
#define to_sc3338(sd) container_of(sd, struct sc3338, subdev)
|
||||
@@ -710,6 +712,9 @@ static long sc3338_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
|
||||
}
|
||||
break;
|
||||
case PREISP_CMD_SET_HDRAE_EXP:
|
||||
if (sc3338->cam_sw_inf)
|
||||
memcpy(&sc3338->cam_sw_inf->hdr_ae, (struct preisp_hdrae_exp_s *)(arg),
|
||||
sizeof(struct preisp_hdrae_exp_s));
|
||||
break;
|
||||
case RKMODULE_SET_QUICK_STREAM:
|
||||
|
||||
@@ -958,6 +963,8 @@ static int __sc3338_power_on(struct sc3338 *sc3338)
|
||||
return ret;
|
||||
}
|
||||
|
||||
cam_sw_regulator_bulk_init(sc3338->cam_sw_inf, SC3338_NUM_SUPPLIES, sc3338->supplies);
|
||||
|
||||
if (sc3338->is_thunderboot)
|
||||
return 0;
|
||||
|
||||
@@ -1024,6 +1031,47 @@ static void __sc3338_power_off(struct sc3338 *sc3338)
|
||||
regulator_bulk_disable(SC3338_NUM_SUPPLIES, sc3338->supplies);
|
||||
}
|
||||
|
||||
#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP)
|
||||
static int sc3338_resume(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct i2c_client *client = to_i2c_client(dev);
|
||||
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
||||
struct sc3338 *sc3338 = to_sc3338(sd);
|
||||
|
||||
cam_sw_prepare_wakeup(sc3338->cam_sw_inf, dev);
|
||||
|
||||
usleep_range(6000, 8000);
|
||||
cam_sw_write_array(sc3338->cam_sw_inf);
|
||||
|
||||
if (__v4l2_ctrl_handler_setup(&sc3338->ctrl_handler))
|
||||
dev_err(dev, "__v4l2_ctrl_handler_setup fail!");
|
||||
|
||||
if (sc3338->has_init_exp && sc3338->cur_mode != NO_HDR) { // hdr mode
|
||||
ret = sc3338_ioctl(&sc3338->subdev, PREISP_CMD_SET_HDRAE_EXP,
|
||||
&sc3338->cam_sw_inf->hdr_ae);
|
||||
if (ret) {
|
||||
dev_err(&sc3338->client->dev, "set exp fail in hdr mode\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sc3338_suspend(struct device *dev)
|
||||
{
|
||||
struct i2c_client *client = to_i2c_client(dev);
|
||||
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
||||
struct sc3338 *sc3338 = to_sc3338(sd);
|
||||
|
||||
cam_sw_write_array_cb_init(sc3338->cam_sw_inf, client,
|
||||
(void *)sc3338->cur_mode->reg_list, (sensor_write_array)sc3338_write_array);
|
||||
cam_sw_prepare_sleep(sc3338->cam_sw_inf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int sc3338_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct i2c_client *client = to_i2c_client(dev);
|
||||
@@ -1082,8 +1130,10 @@ static int sc3338_enum_frame_interval(struct v4l2_subdev *sd,
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops sc3338_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(sc3338_runtime_suspend,
|
||||
sc3338_runtime_resume, NULL)
|
||||
SET_RUNTIME_PM_OPS(sc3338_runtime_suspend, sc3338_runtime_resume, NULL)
|
||||
#if IS_REACHABLE(CONFIG_VIDEO_CAM_SLEEP_WAKEUP)
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(sc3338_suspend, sc3338_resume)
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
||||
@@ -1442,6 +1492,13 @@ static int sc3338_probe(struct i2c_client *client,
|
||||
goto err_power_off;
|
||||
#endif
|
||||
|
||||
if (!sc3338->cam_sw_inf) {
|
||||
sc3338->cam_sw_inf = cam_sw_init();
|
||||
cam_sw_clk_init(sc3338->cam_sw_inf, sc3338->xvclk, SC3338_XVCLK_FREQ);
|
||||
cam_sw_reset_pin_init(sc3338->cam_sw_inf, sc3338->reset_gpio, 0);
|
||||
cam_sw_pwdn_pin_init(sc3338->cam_sw_inf, sc3338->pwdn_gpio, 1);
|
||||
}
|
||||
|
||||
memset(facing, 0, sizeof(facing));
|
||||
if (strcmp(sc3338->module_facing, "back") == 0)
|
||||
facing[0] = 'b';
|
||||
@@ -1492,6 +1549,8 @@ static void sc3338_remove(struct i2c_client *client)
|
||||
v4l2_ctrl_handler_free(&sc3338->ctrl_handler);
|
||||
mutex_destroy(&sc3338->mutex);
|
||||
|
||||
cam_sw_deinit(sc3338->cam_sw_inf);
|
||||
|
||||
pm_runtime_disable(&client->dev);
|
||||
if (!pm_runtime_status_suspended(&client->dev))
|
||||
__sc3338_power_off(sc3338);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
techpoint-objs += techpoint_v4l2.o techpoint_dev.o \
|
||||
techpoint_tp9930.o techpoint_tp2855.o \
|
||||
techpoint_tp9950.o
|
||||
techpoint_tp9950.o techpoint_tp9951.o
|
||||
obj-$(CONFIG_VIDEO_TECHPOINT) += techpoint.o
|
||||
|
||||
@@ -52,6 +52,7 @@ enum techpoint_chips {
|
||||
CHIP_TP2815,
|
||||
CHIP_TP9930,
|
||||
CHIP_TP9950,
|
||||
CHIP_TP9951,
|
||||
};
|
||||
|
||||
enum techpoint_input_type {
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
#include "techpoint_tp9950.h"
|
||||
#include "techpoint_tp2855.h"
|
||||
#include "techpoint_tp2815.h"
|
||||
#include "techpoint_tp9951.h"
|
||||
|
||||
static DEFINE_MUTEX(reg_sem);
|
||||
|
||||
@@ -99,33 +100,40 @@ static int check_chip_id(struct techpoint *techpoint)
|
||||
techpoint_read_reg(client, CHIP_ID_L_REG, &chip_id_l);
|
||||
dev_err(dev, "chip_id_h:0x%2x chip_id_l:0x%2x\n", chip_id_h, chip_id_l);
|
||||
if (chip_id_h == TP9930_CHIP_ID_H_VALUE &&
|
||||
chip_id_l == TP9930_CHIP_ID_L_VALUE) {
|
||||
chip_id_l == TP9930_CHIP_ID_L_VALUE) { //tp2832
|
||||
dev_info(&client->dev,
|
||||
"techpoint check chip id CHIP_TP9930 !\n");
|
||||
techpoint->chip_id = CHIP_TP9930;
|
||||
techpoint->input_type = TECHPOINT_DVP_BT1120;
|
||||
return 0;
|
||||
} else if (chip_id_h == TP2855_CHIP_ID_H_VALUE &&
|
||||
chip_id_l == TP2855_CHIP_ID_L_VALUE) {
|
||||
chip_id_l == TP2855_CHIP_ID_L_VALUE) { //tp2855
|
||||
dev_info(&client->dev,
|
||||
"techpoint check chip id CHIP_TP2855 !\n");
|
||||
techpoint->chip_id = CHIP_TP2855;
|
||||
techpoint->input_type = TECHPOINT_MIPI;
|
||||
return 0;
|
||||
} else if (chip_id_h == TP2815_CHIP_ID_H_VALUE &&
|
||||
chip_id_l == TP2815_CHIP_ID_L_VALUE) {
|
||||
chip_id_l == TP2815_CHIP_ID_L_VALUE) { //tp2815
|
||||
dev_info(&client->dev,
|
||||
"techpoint check chip id CHIP_TP2815 !\n");
|
||||
techpoint->chip_id = CHIP_TP2855;
|
||||
techpoint->input_type = TECHPOINT_MIPI;
|
||||
return 0;
|
||||
} else if (chip_id_h == TP9950_CHIP_ID_H_VALUE &&
|
||||
chip_id_l == TP9950_CHIP_ID_L_VALUE) {
|
||||
chip_id_l == TP9950_CHIP_ID_L_VALUE) { //tp2850
|
||||
dev_info(&client->dev,
|
||||
"techpoint check chip id CHIP_TP9950 !\n");
|
||||
techpoint->chip_id = CHIP_TP9950;
|
||||
techpoint->input_type = TECHPOINT_MIPI;
|
||||
return 0;
|
||||
} else if (chip_id_h == TP9951_CHIP_ID_H_VALUE &&
|
||||
chip_id_l == TP9951_CHIP_ID_L_VALUE) { //tp2860
|
||||
dev_info(&client->dev,
|
||||
"techpoint check chip id CHIP_TP9951 !\n");
|
||||
techpoint->chip_id = CHIP_TP9951;
|
||||
techpoint->input_type = TECHPOINT_MIPI;
|
||||
return 0;
|
||||
}
|
||||
|
||||
dev_info(&client->dev, "techpoint check chip id failed !\n");
|
||||
@@ -143,6 +151,8 @@ int techpoint_initialize_devices(struct techpoint *techpoint)
|
||||
tp2855_initialize(techpoint);
|
||||
else if (techpoint->chip_id == CHIP_TP9950)
|
||||
tp9950_initialize(techpoint);
|
||||
else if (techpoint->chip_id == CHIP_TP9951)
|
||||
tp9951_initialize(techpoint);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -185,6 +195,10 @@ static int detect_thread_function(void *data)
|
||||
detect_status =
|
||||
tp2855_get_channel_input_status
|
||||
(techpoint, i);
|
||||
else if (techpoint->chip_id == CHIP_TP9951)
|
||||
detect_status =
|
||||
tp9951_get_channel_input_status
|
||||
(techpoint, i);
|
||||
|
||||
if (techpoint->detect_status[i] !=
|
||||
detect_status) {
|
||||
@@ -202,8 +216,7 @@ static int detect_thread_function(void *data)
|
||||
else if (techpoint->chip_id == CHIP_TP2855)
|
||||
tp2855_set_decoder_mode(client, i, detect_status);
|
||||
|
||||
techpoint->detect_status[i] =
|
||||
detect_status;
|
||||
techpoint->detect_status[i] = detect_status;
|
||||
need_reset_wait = 5;
|
||||
}
|
||||
}
|
||||
@@ -273,6 +286,11 @@ static __maybe_unused int auto_detect_channel_fmt(struct techpoint *techpoint)
|
||||
tp9950_set_channel_reso(client, 0, reso);
|
||||
}
|
||||
|
||||
if (techpoint->chip_id == CHIP_TP9951) {
|
||||
reso = tp9951_get_channel_reso(client, 0);
|
||||
tp9951_set_channel_reso(client, 0, reso);
|
||||
}
|
||||
|
||||
mutex_unlock(®_sem);
|
||||
|
||||
return 0;
|
||||
|
||||
638
drivers/media/i2c/techpoint/techpoint_tp9951.c
Normal file
638
drivers/media/i2c/techpoint/techpoint_tp9951.c
Normal file
@@ -0,0 +1,638 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* techpoint lib
|
||||
*
|
||||
* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "techpoint_tp9951.h"
|
||||
#include "techpoint_dev.h"
|
||||
|
||||
static struct techpoint_video_modes supported_modes[] = {
|
||||
#if TP9951_DEF_PAL
|
||||
{
|
||||
.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
|
||||
.width = 960,
|
||||
.height = 576,
|
||||
.max_fps = {
|
||||
.numerator = 10000,
|
||||
.denominator = 250000,
|
||||
},
|
||||
.link_freq_value = TP9951_LINK_FREQ_148M,
|
||||
.common_reg_list = NULL,
|
||||
.common_reg_size = 0,
|
||||
.bpp = TP9951_BITS_PER_SAMPLE,
|
||||
.lane = TP9951_LANES,
|
||||
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
||||
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
|
||||
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
|
||||
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
|
||||
},
|
||||
#endif
|
||||
#if TP9951_DEF_NTSC
|
||||
{
|
||||
.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
|
||||
.width = 960,
|
||||
.height = 480,
|
||||
.max_fps = {
|
||||
.numerator = 10000,
|
||||
.denominator = 250000,
|
||||
},
|
||||
.link_freq_value = TP9951_LINK_FREQ_148M,
|
||||
.common_reg_list = NULL,
|
||||
.common_reg_size = 0,
|
||||
.bpp = TP9951_BITS_PER_SAMPLE,
|
||||
.lane = TP9951_LANES,
|
||||
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
||||
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
|
||||
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
|
||||
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
|
||||
},
|
||||
#endif
|
||||
#if TP9951_DEF_1080P
|
||||
{
|
||||
.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
|
||||
.width = 1920,
|
||||
.height = 1080,
|
||||
.max_fps = {
|
||||
.numerator = 10000,
|
||||
.denominator = 250000,
|
||||
},
|
||||
// .link_freq_value = TP9951_LINK_FREQ_594M,
|
||||
.link_freq_value = TP9951_LINK_FREQ_297M,
|
||||
.common_reg_list = NULL,
|
||||
.common_reg_size = 0,
|
||||
.bpp = TP9951_BITS_PER_SAMPLE,
|
||||
.lane = TP9951_LANES,
|
||||
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
||||
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
|
||||
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
|
||||
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
|
||||
},
|
||||
#endif
|
||||
#if TP9951_DEF_720P
|
||||
{
|
||||
.bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
|
||||
.width = 1280,
|
||||
.height = 720,
|
||||
.max_fps = {
|
||||
.numerator = 10000,
|
||||
.denominator = 250000,
|
||||
},
|
||||
.link_freq_value = TP9951_LINK_FREQ_297M,
|
||||
.common_reg_list = NULL,
|
||||
.common_reg_size = 0,
|
||||
.bpp = TP9951_BITS_PER_SAMPLE,
|
||||
.lane = TP9951_LANES,
|
||||
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
|
||||
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
|
||||
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
|
||||
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int tp9951_initialize(struct techpoint *techpoint)
|
||||
{
|
||||
int array_size = 0;
|
||||
struct i2c_client *client = techpoint->client;
|
||||
struct device *dev = &client->dev;
|
||||
|
||||
techpoint->video_modes_num = ARRAY_SIZE(supported_modes);
|
||||
array_size =
|
||||
sizeof(struct techpoint_video_modes) * techpoint->video_modes_num;
|
||||
techpoint->video_modes = devm_kzalloc(dev, array_size, GFP_KERNEL);
|
||||
memcpy(techpoint->video_modes, supported_modes, array_size);
|
||||
|
||||
techpoint->cur_video_mode = &techpoint->video_modes[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tp9951_get_channel_input_status(struct techpoint *techpoint, u8 ch)
|
||||
{
|
||||
u8 val = 0;
|
||||
struct i2c_client *client = techpoint->client;
|
||||
|
||||
if (ch != 0) // tp9951 just support 1 chn
|
||||
return 0;
|
||||
techpoint_write_reg(client, PAGE_REG, ch);
|
||||
techpoint_read_reg(client, INPUT_STATUS_REG, &val);
|
||||
dev_dbg(&client->dev, "input_status ch %d : %x\n", ch, val);
|
||||
|
||||
return (val & INPUT_STATUS_MASK) ? 0 : 1;
|
||||
}
|
||||
|
||||
int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status)
|
||||
{
|
||||
u8 val = 0;
|
||||
struct i2c_client *client = techpoint->client;
|
||||
|
||||
// tp9951 just support 1 chn
|
||||
techpoint_write_reg(client, PAGE_REG, 0);
|
||||
techpoint_read_reg(client, INPUT_STATUS_REG, &val);
|
||||
detect_status[0] = tp9951_get_channel_input_status(techpoint, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tp9951_set_mipi_out(struct i2c_client *client,
|
||||
enum techpoint_support_reso reso,
|
||||
unsigned char lane)
|
||||
{
|
||||
u8 tmp;
|
||||
//mipi setting
|
||||
techpoint_write_reg(client, 0x40, 0x08); //select MIPI page
|
||||
techpoint_write_reg(client, 0x02, 0x7d);
|
||||
techpoint_write_reg(client, 0x03, 0x75);
|
||||
techpoint_write_reg(client, 0x04, 0x75);
|
||||
techpoint_write_reg(client, 0x13, 0xef);
|
||||
techpoint_write_reg(client, 0x20, 0x00);
|
||||
techpoint_write_reg(client, 0x23, 0x9e);
|
||||
|
||||
if (lane == MIPI_1LANE) {
|
||||
techpoint_write_reg(client, 0x21, 0x11);
|
||||
|
||||
if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
|
||||
techpoint_write_reg(client, 0x12, 0x54);
|
||||
techpoint_write_reg(client, 0x14, 0x00);
|
||||
techpoint_write_reg(client, 0x15, 0x02);
|
||||
|
||||
techpoint_write_reg(client, 0x2a, 0x08);
|
||||
techpoint_write_reg(client, 0x2b, 0x06);
|
||||
techpoint_write_reg(client, 0x2c, 0x12);
|
||||
techpoint_write_reg(client, 0x2e, 0x0a);
|
||||
} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
|
||||
techpoint_write_reg(client, 0x12, 0x54);
|
||||
techpoint_write_reg(client, 0x14, 0x00);
|
||||
techpoint_write_reg(client, 0x15, 0x12);
|
||||
|
||||
techpoint_write_reg(client, 0x2a, 0x04);
|
||||
techpoint_write_reg(client, 0x2b, 0x03);
|
||||
techpoint_write_reg(client, 0x2c, 0x0a);
|
||||
techpoint_write_reg(client, 0x2e, 0x02);
|
||||
} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
|
||||
techpoint_write_reg(client, 0x12, 0x54);
|
||||
techpoint_write_reg(client, 0x14, 0x51);
|
||||
techpoint_write_reg(client, 0x15, 0x07);
|
||||
|
||||
techpoint_write_reg(client, 0x2a, 0x02);
|
||||
techpoint_write_reg(client, 0x2b, 0x01);
|
||||
techpoint_write_reg(client, 0x2c, 0x06);
|
||||
techpoint_write_reg(client, 0x2e, 0x02);
|
||||
}
|
||||
} else { // 2 lane
|
||||
techpoint_write_reg(client, 0x21, 0x12);
|
||||
|
||||
if (TECHPOINT_S_RESO_1080P_30 == reso || TECHPOINT_S_RESO_1080P_25 == reso) {
|
||||
techpoint_write_reg(client, 0x12, 0x54);
|
||||
techpoint_write_reg(client, 0x14, 0x41);
|
||||
techpoint_write_reg(client, 0x15, 0x02);
|
||||
|
||||
techpoint_write_reg(client, 0x2a, 0x04);
|
||||
techpoint_write_reg(client, 0x2b, 0x03);
|
||||
techpoint_write_reg(client, 0x2c, 0x0a);
|
||||
techpoint_write_reg(client, 0x2e, 0x02);
|
||||
} else if (TECHPOINT_S_RESO_720P_30 == reso || TECHPOINT_S_RESO_720P_25 == reso) {
|
||||
techpoint_write_reg(client, 0x12, 0x54);
|
||||
techpoint_write_reg(client, 0x14, 0x41);
|
||||
techpoint_write_reg(client, 0x15, 0x12);
|
||||
|
||||
techpoint_write_reg(client, 0x2a, 0x02);
|
||||
techpoint_write_reg(client, 0x2b, 0x01);
|
||||
techpoint_write_reg(client, 0x2c, 0x06);
|
||||
techpoint_write_reg(client, 0x2e, 0x02);
|
||||
} else if (TECHPOINT_S_RESO_NTSC == reso || TECHPOINT_S_RESO_PAL == reso) {
|
||||
techpoint_write_reg(client, 0x12, 0x54);
|
||||
techpoint_write_reg(client, 0x14, 0x62);
|
||||
techpoint_write_reg(client, 0x15, 0x07);
|
||||
|
||||
techpoint_write_reg(client, 0x2a, 0x02);
|
||||
techpoint_write_reg(client, 0x2b, 0x00);
|
||||
techpoint_write_reg(client, 0x2c, 0x04);
|
||||
techpoint_write_reg(client, 0x2e, 0x02);
|
||||
}
|
||||
}
|
||||
|
||||
techpoint_write_reg(client, 0x40, 0x00); //back to decoder page
|
||||
techpoint_read_reg(client, 0x06, &tmp); //PLL reset
|
||||
techpoint_write_reg(client, 0x06, 0x80 | tmp);
|
||||
|
||||
techpoint_write_reg(client, 0x40, 0x08); //back to mipi page
|
||||
|
||||
techpoint_read_reg(client, 0x14, &tmp); //PLL reset
|
||||
techpoint_write_reg(client, 0x14, 0x80 | tmp);
|
||||
techpoint_write_reg(client, 0x14, tmp);
|
||||
|
||||
/* Enable MIPI CSI2 output */
|
||||
techpoint_write_reg(client, 0x28, 0x02); //stream off
|
||||
techpoint_write_reg(client, 0x28, 0x00); //stream on
|
||||
techpoint_write_reg(client, 0x40, 0x00); //back to decoder page
|
||||
}
|
||||
|
||||
int tp9951_set_channel_reso(struct i2c_client *client, int ch,
|
||||
enum techpoint_support_reso reso)
|
||||
{
|
||||
int val = reso;
|
||||
|
||||
dev_info(&client->dev, "##$$ %s", __func__);
|
||||
techpoint_write_reg(client, 0x40, 0x00); //select decoder page
|
||||
techpoint_write_reg(client, 0x06, 0x12); //default value
|
||||
techpoint_write_reg(client, 0x42, 0x00); //common setting for all format
|
||||
techpoint_write_reg(client, 0x4e, 0x00); //common setting for MIPI output
|
||||
techpoint_write_reg(client, 0x54, 0x00); //common setting for MIPI output
|
||||
techpoint_write_reg(client, 0x41, ch); //video MUX select
|
||||
|
||||
switch (val) {
|
||||
case TECHPOINT_S_RESO_720P_25:
|
||||
#if TP9951_DEF_720P
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "set channel 720P_25\n");
|
||||
techpoint_write_reg(client, 0x02, 0x42);
|
||||
techpoint_write_reg(client, 0x07, 0xc0);
|
||||
techpoint_write_reg(client, 0x0b, 0xc0);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x13);
|
||||
techpoint_write_reg(client, 0x16, 0x15);
|
||||
techpoint_write_reg(client, 0x17, 0x00);
|
||||
techpoint_write_reg(client, 0x18, 0x19);
|
||||
techpoint_write_reg(client, 0x19, 0xd0);
|
||||
techpoint_write_reg(client, 0x1a, 0x25);
|
||||
techpoint_write_reg(client, 0x1c, 0x07);//1280*720, 25fps
|
||||
techpoint_write_reg(client, 0x1d, 0xbc);//1280*720, 25fps
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x30);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x60);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x30);
|
||||
techpoint_write_reg(client, 0x2e, 0x70);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x48);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x2e);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
techpoint_write_reg(client, 0x35, 0x25);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x18);
|
||||
if (STD_HDA) {
|
||||
techpoint_write_reg(client, 0x02, 0x46);
|
||||
techpoint_write_reg(client, 0x0d, 0x71);
|
||||
techpoint_write_reg(client, 0x18, 0x1b);
|
||||
techpoint_write_reg(client, 0x20, 0x40);
|
||||
techpoint_write_reg(client, 0x21, 0x46);
|
||||
techpoint_write_reg(client, 0x25, 0xfe);
|
||||
techpoint_write_reg(client, 0x26, 0x01);
|
||||
techpoint_write_reg(client, 0x2c, 0x3a);
|
||||
techpoint_write_reg(client, 0x2d, 0x5a);
|
||||
techpoint_write_reg(client, 0x2e, 0x40);
|
||||
techpoint_write_reg(client, 0x30, 0x9e);
|
||||
techpoint_write_reg(client, 0x31, 0x20);
|
||||
techpoint_write_reg(client, 0x32, 0x10);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
}
|
||||
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
|
||||
break;
|
||||
case TECHPOINT_S_RESO_1080P_25: // FHD25
|
||||
#if TP9951_DEF_1080P
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "set channel 1080P_25\n");
|
||||
techpoint_write_reg(client, 0x02, 0x40);
|
||||
techpoint_write_reg(client, 0x07, 0xc0);
|
||||
techpoint_write_reg(client, 0x0b, 0xc0);
|
||||
techpoint_write_reg(client, 0x0c, 0x03);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xd2);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x29);
|
||||
techpoint_write_reg(client, 0x19, 0x38);
|
||||
techpoint_write_reg(client, 0x1a, 0x47);
|
||||
techpoint_write_reg(client, 0x1c, 0x0a);//1920*1080, 25fps
|
||||
techpoint_write_reg(client, 0x1d, 0x50);//
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x30);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x60);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x30);
|
||||
techpoint_write_reg(client, 0x2e, 0x70);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x48);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x2e);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
techpoint_write_reg(client, 0x35, 0x05);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x1C);
|
||||
if (STD_HDA) {
|
||||
techpoint_write_reg(client, 0x02, 0x44);
|
||||
techpoint_write_reg(client, 0x0d, 0x73);
|
||||
techpoint_write_reg(client, 0x15, 0x01);
|
||||
techpoint_write_reg(client, 0x16, 0xf0);
|
||||
techpoint_write_reg(client, 0x18, 0x2a);
|
||||
techpoint_write_reg(client, 0x20, 0x3c);
|
||||
techpoint_write_reg(client, 0x21, 0x46);
|
||||
techpoint_write_reg(client, 0x25, 0xfe);
|
||||
techpoint_write_reg(client, 0x26, 0x0d);
|
||||
techpoint_write_reg(client, 0x2c, 0x3a);
|
||||
techpoint_write_reg(client, 0x2d, 0x54);
|
||||
techpoint_write_reg(client, 0x2e, 0x40);
|
||||
techpoint_write_reg(client, 0x30, 0xa5);
|
||||
techpoint_write_reg(client, 0x31, 0x86);
|
||||
techpoint_write_reg(client, 0x32, 0xfb);
|
||||
techpoint_write_reg(client, 0x33, 0x60);
|
||||
}
|
||||
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
|
||||
break;
|
||||
case TECHPOINT_S_RESO_1080P_30: // FHD30
|
||||
dev_err(&client->dev, "set channel PAL\n");
|
||||
techpoint_write_reg(client, 0x02, 0x40);
|
||||
techpoint_write_reg(client, 0x07, 0xc0);
|
||||
techpoint_write_reg(client, 0x0b, 0xc0);
|
||||
techpoint_write_reg(client, 0x0c, 0x03);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xd2);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x29);
|
||||
techpoint_write_reg(client, 0x19, 0x38);
|
||||
techpoint_write_reg(client, 0x1a, 0x47);
|
||||
techpoint_write_reg(client, 0x1c, 0x08); //1920*1080, 30fps
|
||||
techpoint_write_reg(client, 0x1d, 0x98); //
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x30);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x60);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x30);
|
||||
techpoint_write_reg(client, 0x2e, 0x70);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x48);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x2e);
|
||||
techpoint_write_reg(client, 0x33, 0x90);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x05);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x1C);
|
||||
|
||||
if (STD_HDA) { //AHD1080p30 extra
|
||||
techpoint_write_reg(client, 0x02, 0x44);
|
||||
techpoint_write_reg(client, 0x0d, 0x72);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x01);
|
||||
techpoint_write_reg(client, 0x16, 0xf0);
|
||||
techpoint_write_reg(client, 0x18, 0x2a);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x38);
|
||||
techpoint_write_reg(client, 0x21, 0x46);
|
||||
|
||||
techpoint_write_reg(client, 0x25, 0xfe);
|
||||
techpoint_write_reg(client, 0x26, 0x0d);
|
||||
|
||||
techpoint_write_reg(client, 0x2c, 0x3a);
|
||||
techpoint_write_reg(client, 0x2d, 0x54);
|
||||
techpoint_write_reg(client, 0x2e, 0x40);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0xa5);
|
||||
techpoint_write_reg(client, 0x31, 0x95);
|
||||
techpoint_write_reg(client, 0x32, 0xe0);
|
||||
techpoint_write_reg(client, 0x33, 0x60);
|
||||
}
|
||||
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
break;
|
||||
|
||||
case TECHPOINT_S_RESO_PAL:
|
||||
#if TP9951_DEF_PAL
|
||||
default:
|
||||
#endif
|
||||
|
||||
#if CVBS_960H
|
||||
dev_err(&client->dev, "set channel CVBS_960H\n");
|
||||
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x51);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x13);
|
||||
techpoint_write_reg(client, 0x16, 0x76);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x17);
|
||||
techpoint_write_reg(client, 0x19, 0x20);
|
||||
techpoint_write_reg(client, 0x1a, 0x17);
|
||||
techpoint_write_reg(client, 0x1c, 0x09);
|
||||
techpoint_write_reg(client, 0x1d, 0x48);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x48);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x37);
|
||||
techpoint_write_reg(client, 0x23, 0x3f);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x64);
|
||||
techpoint_write_reg(client, 0x2e, 0x56);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x7a);
|
||||
techpoint_write_reg(client, 0x31, 0x4a);
|
||||
techpoint_write_reg(client, 0x32, 0x4d);
|
||||
techpoint_write_reg(client, 0x33, 0xf0);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
|
||||
#else //PAL 720H
|
||||
dev_err(&client->dev, "set channel PAL 720H\n");
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x06, 0x32);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x51);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xf0);
|
||||
techpoint_write_reg(client, 0x17, 0xa0);
|
||||
techpoint_write_reg(client, 0x18, 0x17);
|
||||
techpoint_write_reg(client, 0x19, 0x20);
|
||||
techpoint_write_reg(client, 0x1a, 0x15);
|
||||
techpoint_write_reg(client, 0x1c, 0x06);
|
||||
techpoint_write_reg(client, 0x1d, 0xc0);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x48);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x37);
|
||||
techpoint_write_reg(client, 0x23, 0x3f);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x4b);
|
||||
techpoint_write_reg(client, 0x2e, 0x56);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x7a);
|
||||
techpoint_write_reg(client, 0x31, 0x4a);
|
||||
techpoint_write_reg(client, 0x32, 0x4d);
|
||||
techpoint_write_reg(client, 0x33, 0xfb);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
#endif
|
||||
tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
|
||||
|
||||
break;
|
||||
case TECHPOINT_S_RESO_NTSC:
|
||||
#if TP9951_DEF_NTSC
|
||||
default:
|
||||
#endif
|
||||
|
||||
#if CVBS_960H
|
||||
dev_err(&client->dev, "set channel NTSC CVBS_960H\n");
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x13);
|
||||
techpoint_write_reg(client, 0x16, 0x60);
|
||||
techpoint_write_reg(client, 0x17, 0x80);
|
||||
techpoint_write_reg(client, 0x18, 0x12);
|
||||
techpoint_write_reg(client, 0x19, 0xf0);
|
||||
techpoint_write_reg(client, 0x1a, 0x07);
|
||||
techpoint_write_reg(client, 0x1c, 0x09);
|
||||
techpoint_write_reg(client, 0x1d, 0x38);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x40);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x68);
|
||||
techpoint_write_reg(client, 0x2e, 0x57);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x62);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x96);
|
||||
techpoint_write_reg(client, 0x33, 0xc0);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
#else
|
||||
dev_err(&client->dev, "set channel NTSC 720H\n");
|
||||
techpoint_write_reg(client, 0x02, 0x47);
|
||||
techpoint_write_reg(client, 0x0c, 0x13);
|
||||
techpoint_write_reg(client, 0x0d, 0x50);
|
||||
|
||||
techpoint_write_reg(client, 0x15, 0x03);
|
||||
techpoint_write_reg(client, 0x16, 0xd6);
|
||||
techpoint_write_reg(client, 0x17, 0xa0);
|
||||
techpoint_write_reg(client, 0x18, 0x12);
|
||||
techpoint_write_reg(client, 0x19, 0xf0);
|
||||
techpoint_write_reg(client, 0x1a, 0x05);
|
||||
techpoint_write_reg(client, 0x1c, 0x06);
|
||||
techpoint_write_reg(client, 0x1d, 0xb4);
|
||||
|
||||
techpoint_write_reg(client, 0x20, 0x40);
|
||||
techpoint_write_reg(client, 0x21, 0x84);
|
||||
techpoint_write_reg(client, 0x22, 0x36);
|
||||
techpoint_write_reg(client, 0x23, 0x3c);
|
||||
|
||||
techpoint_write_reg(client, 0x2b, 0x70);
|
||||
techpoint_write_reg(client, 0x2c, 0x2a);
|
||||
techpoint_write_reg(client, 0x2d, 0x4b);
|
||||
techpoint_write_reg(client, 0x2e, 0x57);
|
||||
|
||||
techpoint_write_reg(client, 0x30, 0x62);
|
||||
techpoint_write_reg(client, 0x31, 0xbb);
|
||||
techpoint_write_reg(client, 0x32, 0x96);
|
||||
techpoint_write_reg(client, 0x33, 0xcb);
|
||||
|
||||
techpoint_write_reg(client, 0x35, 0x65);
|
||||
techpoint_write_reg(client, 0x38, 0x00);
|
||||
techpoint_write_reg(client, 0x39, 0x04);
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
|
||||
#if TECHPOINT_TEST_PATTERN
|
||||
techpoint_write_reg(client, 0x2a, 0x3c);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
// detect for reference only, the accuracy may be affected by the current invoked decoding standard.
|
||||
int tp9951_get_channel_reso(struct i2c_client *client, int ch)
|
||||
{
|
||||
u8 detect_fmt = 0xff;
|
||||
u8 reso = 0xff;
|
||||
|
||||
techpoint_write_reg(client, 0x40, ch);
|
||||
techpoint_read_reg(client, 0x03, &detect_fmt);
|
||||
reso = detect_fmt & 0x7;
|
||||
|
||||
switch (reso) {
|
||||
case TP9951_CVSTD_720P_25:
|
||||
#if TP9951_DEF_720P
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d 720P_25\n", ch);
|
||||
return TECHPOINT_S_RESO_720P_25;
|
||||
case TP9951_CVSTD_1080P_25:
|
||||
#if TP9951_DEF_1080P
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d 1080P_25\n", ch);
|
||||
return TECHPOINT_S_RESO_1080P_25;
|
||||
case TP9951_CVSTD_PAL:
|
||||
#if TP9951_DEF_PAL
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d PAL\n", ch);
|
||||
return TECHPOINT_S_RESO_PAL;
|
||||
case TP9951_CVSTD_NTSC:
|
||||
#if TP9951_DEF_NTSC
|
||||
default:
|
||||
#endif
|
||||
dev_err(&client->dev, "detect channel %d NTSC\n", ch);
|
||||
return TECHPOINT_S_RESO_NTSC;
|
||||
}
|
||||
|
||||
return reso;
|
||||
}
|
||||
|
||||
int tp9951_set_quick_stream(struct i2c_client *client, u32 stream)
|
||||
{
|
||||
// mutex_lock(&techpoint->mutex);
|
||||
if (stream) {
|
||||
techpoint_write_reg(client, 0x40, 0x8);
|
||||
techpoint_write_reg(client, 0x28, 0x0);
|
||||
} else {
|
||||
techpoint_write_reg(client, 0x40, 0x8);
|
||||
techpoint_write_reg(client, 0x28, 0x2);
|
||||
usleep_range(40 * 1000, 50 * 1000);
|
||||
}
|
||||
// mutex_unlock(&techpoint->mutex);
|
||||
return 0;
|
||||
}
|
||||
76
drivers/media/i2c/techpoint/techpoint_tp9951.h
Normal file
76
drivers/media/i2c/techpoint/techpoint_tp9951.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* techpoint tp9951 regs
|
||||
*
|
||||
* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _TECHPOINT_TP9951_H
|
||||
#define _TECHPOINT_TP9951_H
|
||||
|
||||
#include "techpoint_common.h"
|
||||
|
||||
#define DEBUG
|
||||
|
||||
#define TP9951_DEF_1080P 1
|
||||
#define TP9951_DEF_720P 0
|
||||
#define TP9951_DEF_PAL 0
|
||||
#define TP9951_DEF_NTSC 0
|
||||
|
||||
#define STD_TVI 0
|
||||
#define STD_HDA 1
|
||||
|
||||
// device id 0x2860
|
||||
#define TP9951_CHIP_ID_H_REG 0xFE
|
||||
#define TP9951_CHIP_ID_H_VALUE 0x28
|
||||
#define TP9951_CHIP_ID_L_REG 0xFF
|
||||
#define TP9951_CHIP_ID_L_VALUE 0x60
|
||||
|
||||
#define TP9951_LINK_FREQ_148M (148500000UL >> 1)
|
||||
#define TP9951_LINK_FREQ_297M (297000000UL >> 1)
|
||||
#define TP9951_LINK_FREQ_594M (594000000UL >> 1)
|
||||
#define TP9951_LANES 2
|
||||
#define TP9951_BITS_PER_SAMPLE 8
|
||||
|
||||
enum tp9952_support_mipi_lane {
|
||||
MIPI_2LANE,
|
||||
MIPI_1LANE,
|
||||
};
|
||||
|
||||
#define CVBS_960H (0) //1->960H 0->720H
|
||||
|
||||
enum tp9951_support_reso {
|
||||
TP9951_CVSTD_720P_60 = 0,
|
||||
TP9951_CVSTD_720P_50,
|
||||
TP9951_CVSTD_1080P_30,
|
||||
TP9951_CVSTD_1080P_25,
|
||||
TP9951_CVSTD_720P_30,
|
||||
TP9951_CVSTD_720P_25,
|
||||
TP9951_CVSTD_SD,
|
||||
TP9951_CVSTD_OTHER,
|
||||
TP9951_CVSTD_720P_275,
|
||||
TP9951_CVSTD_QHD30, //960×540 only support with 2lane mode
|
||||
TP9951_CVSTD_QHD25, //960×540 only support with 2lane mode
|
||||
TP9951_CVSTD_PAL,
|
||||
TP9951_CVSTD_NTSC,
|
||||
TP9951_CVSTD_UVGA25, //1280x960p25, must use with MIPI_4CH4LANE_445M
|
||||
TP9951_CVSTD_UVGA30, //1280x960p30, must use with MIPI_4CH4LANE_445M
|
||||
TP9951_CVSTD_A_UVGA30, //HDA 1280x960p30, must use with MIPI_4CH4LANE_378M
|
||||
TP9951_CVSTD_F_UVGA30, //FH 1280x960p30, 1800x1000
|
||||
TP9951_CVSTD_HD30864, //total 1600x900 86.4M
|
||||
TP9951_CVSTD_HD30HDR, //special 720p30 with ISX019/SC120AT,total 1650x900
|
||||
TP9951_CVSTD_1080P_60,//only support with 2lane mode
|
||||
TP9951_CVSTD_1080P_50,//only support with 2lane mode
|
||||
TP9951_CVSTD_1080P_28,
|
||||
TP9951_CVSTD_1080P_275,
|
||||
};
|
||||
|
||||
int tp9951_initialize(struct techpoint *techpoint);
|
||||
int tp9951_get_channel_input_status(struct techpoint *techpoint, u8 ch);
|
||||
int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status);
|
||||
int tp9951_set_channel_reso(struct i2c_client *client, int ch,
|
||||
enum techpoint_support_reso reso);
|
||||
int tp9951_get_channel_reso(struct i2c_client *client, int ch);
|
||||
int tp9951_set_quick_stream(struct i2c_client *client, u32 stream);
|
||||
|
||||
#endif // _TECHPOINT_TP9951_H
|
||||
@@ -854,6 +854,7 @@ static const struct of_device_id techpoint_of_match[] = {
|
||||
{ .compatible = "techpoint,tp2815" },
|
||||
{ .compatible = "techpoint,tp9930" },
|
||||
{ .compatible = "techpoint,tp9950" },
|
||||
{ .compatible = "techpoint,tp9951" },
|
||||
{ },
|
||||
};
|
||||
|
||||
@@ -1290,7 +1291,6 @@ static int techpoint_audio_probe(struct techpoint *techpoint)
|
||||
}
|
||||
|
||||
if (techpoint->chip_id == CHIP_TP9930) {
|
||||
|
||||
techpoint_write_reg(techpoint->client, 0x40, 0x00);
|
||||
for (i = 0; i < 0xff; i++)
|
||||
techpoint_write_reg(techpoint->client, i, 0xbb);
|
||||
|
||||
@@ -459,6 +459,30 @@
|
||||
* 11.fix image effect for frame two-run
|
||||
* 12.fix underperformance for frame two-run
|
||||
* 13.support unite mode for isp32
|
||||
*
|
||||
* v2.4.0 (AIQ v5.4.0)
|
||||
* 1.fix rv1106g3 4k cmsk right
|
||||
* 2.fix image effect for rv1106 4k
|
||||
* 3.add RKISP_VICAP_CMD_QUICK_STREAM CMD
|
||||
* 4.support suspend and resume
|
||||
* 5.pm add call sensor s_power
|
||||
* 6.suspend resume with rtt
|
||||
* 7.fix resume hold by lut error
|
||||
* 8.fix rv1106g3 4k can't cmsk rightmost
|
||||
* 9.fix rv1106 resume no output
|
||||
* 10.support to do reset in online mode
|
||||
* 11.support change work mode to online with quick stream
|
||||
* 12.fix build warning
|
||||
* 13.frame timestamp change to sof
|
||||
* 14.fix wnd_num cause array access out of bounds
|
||||
* 15.fix rv1106 cycle kill rkipc null pointer
|
||||
* 16.fix power_cnt if error
|
||||
* 17.fix rockit set_fmt stuck
|
||||
* 18.fix info2ddr no enable
|
||||
* 19.fix reset can't open
|
||||
* 20.more time to wait isp end
|
||||
* 21.add mode for rv1106 suspend without rtt
|
||||
* 22.fix is_on false cause pm isp die
|
||||
*/
|
||||
|
||||
#define RKISP_DRIVER_VERSION RKISP_API_VERSION
|
||||
|
||||
@@ -528,18 +528,18 @@ static void rockchip_pcie_resize_bar(struct rockchip_pcie *rockchip)
|
||||
|
||||
/* Resize BAR0 4M 32bits, BAR2 64M 64bits-pref, BAR4 1MB 32bits */
|
||||
bar = BAR_0;
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x40);
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x2c0);
|
||||
rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
|
||||
|
||||
bar = BAR_2;
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x400);
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0x6c0);
|
||||
rockchip_pcie_ep_set_bar_flag(rockchip, bar,
|
||||
PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
|
||||
|
||||
bar = BAR_4;
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0xfffff0);
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x4 + bar * 0x8, 0x10);
|
||||
dw_pcie_writel_dbi(pci, resbar_base + 0x8 + bar * 0x8, 0xc0);
|
||||
rockchip_pcie_ep_set_bar_flag(rockchip, bar, PCI_BASE_ADDRESS_MEM_TYPE_32);
|
||||
|
||||
@@ -970,27 +970,12 @@ static int pcie_ep_release(struct inode *inode, struct file *file)
|
||||
static long pcie_ep_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
struct rockchip_pcie *rockchip = (struct rockchip_pcie *)file->private_data;
|
||||
struct pcie_ep_user_data msg;
|
||||
struct pcie_ep_dma_cache_cfg cfg;
|
||||
void __user *uarg = (void __user *)arg;
|
||||
int i, ret;
|
||||
enum pcie_ep_mmap_resource mmap_res;
|
||||
|
||||
switch (cmd) {
|
||||
case PCIE_DMA_GET_ELBI_DATA:
|
||||
for (i = 4; i <= 6; i++)
|
||||
msg.elbi_app_user[i - 4] = dw_pcie_readl_dbi(&rockchip->pci,
|
||||
PCIE_ELBI_LOCAL_BASE + i * 4);
|
||||
for (i = 8; i <= 15; i++)
|
||||
msg.elbi_app_user[i - 5] = dw_pcie_readl_dbi(&rockchip->pci,
|
||||
PCIE_ELBI_LOCAL_BASE + i * 4);
|
||||
|
||||
ret = copy_to_user(uarg, &msg, sizeof(msg));
|
||||
if (ret) {
|
||||
dev_err(rockchip->pci.dev, "failed to get elbi data\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
break;
|
||||
case PCIE_DMA_CACHE_INVALIDE:
|
||||
ret = copy_from_user(&cfg, uarg, sizeof(cfg));
|
||||
if (ret) {
|
||||
@@ -1017,15 +1002,6 @@ static long pcie_ep_ioctl(struct file *file, unsigned int cmd, unsigned long arg
|
||||
rockchip->obj_info->irq_type_rc = OBJ_IRQ_USER;
|
||||
rockchip_pcie_raise_msi_irq(rockchip, PCIe_CLIENT_MSI_OBJ_IRQ);
|
||||
break;
|
||||
case PCIE_EP_GET_USER_INFO:
|
||||
msg.bar0_phys_addr = rockchip->ib_target_address[0];
|
||||
|
||||
ret = copy_to_user(uarg, &msg, sizeof(msg));
|
||||
if (ret) {
|
||||
dev_err(rockchip->pci.dev, "failed to get elbi data\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
break;
|
||||
case PCIE_EP_SET_MMAP_RESOURCE:
|
||||
ret = copy_from_user(&mmap_res, uarg, sizeof(mmap_res));
|
||||
if (ret) {
|
||||
|
||||
@@ -11,7 +11,7 @@
|
||||
#include <linux/types.h>
|
||||
#include <linux/v4l2-controls.h>
|
||||
|
||||
#define RKISP_API_VERSION KERNEL_VERSION(2, 3, 0)
|
||||
#define RKISP_API_VERSION KERNEL_VERSION(2, 4, 0)
|
||||
|
||||
/****************ISP SUBDEV IOCTL*****************************/
|
||||
|
||||
|
||||
@@ -24,14 +24,6 @@
|
||||
/* Application status*/
|
||||
#define RKEP_SMODE_APPRDY 0x20
|
||||
|
||||
/*
|
||||
* rockchip pcie driver elbi ioctrl output data
|
||||
*/
|
||||
struct pcie_ep_user_data {
|
||||
__u64 bar0_phys_addr;
|
||||
__u32 elbi_app_user[11];
|
||||
};
|
||||
|
||||
/*
|
||||
* rockchip driver cache ioctrl input param
|
||||
*/
|
||||
@@ -101,12 +93,10 @@ struct pcie_ep_obj_info {
|
||||
};
|
||||
|
||||
#define PCIE_BASE 'P'
|
||||
#define PCIE_DMA_GET_ELBI_DATA _IOR(PCIE_BASE, 0, struct pcie_ep_user_data)
|
||||
#define PCIE_DMA_CACHE_INVALIDE _IOW(PCIE_BASE, 1, struct pcie_ep_dma_cache_cfg)
|
||||
#define PCIE_DMA_CACHE_FLUSH _IOW(PCIE_BASE, 2, struct pcie_ep_dma_cache_cfg)
|
||||
#define PCIE_DMA_IRQ_MASK_ALL _IOW(PCIE_BASE, 3, int)
|
||||
#define PCIE_DMA_RAISE_MSI_OBJ_IRQ_USER _IOW(PCIE_BASE, 4, int)
|
||||
#define PCIE_EP_GET_USER_INFO _IOR(PCIE_BASE, 5, struct pcie_ep_user_data)
|
||||
#define PCIE_EP_SET_MMAP_RESOURCE _IOW(PCIE_BASE, 6, int)
|
||||
#define PCIE_EP_RAISE_ELBI _IOW(PCIE_BASE, 7, int)
|
||||
#define PCIE_EP_REQUEST_VIRTUAL_ID _IOR(PCIE_BASE, 16, int)
|
||||
|
||||
Reference in New Issue
Block a user