clk: rockchip: px30: add more setting of cpu-clk

Change-Id: Ie3f22964f16a636c33c5b215afb6ac8ddd653918
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2018-02-10 10:33:19 +08:00
committed by Tao Huang
parent bd5e33aeb5
commit 2e0c97d607

View File

@@ -102,11 +102,22 @@ static struct rockchip_pll_rate_table px30_pll_rates[] = {
static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
PX30_CPUCLK_RATE(1608000000, 1, 7),
PX30_CPUCLK_RATE(1584000000, 1, 7),
PX30_CPUCLK_RATE(1560000000, 1, 7),
PX30_CPUCLK_RATE(1536000000, 1, 7),
PX30_CPUCLK_RATE(1512000000, 1, 7),
PX30_CPUCLK_RATE(1488000000, 1, 5),
PX30_CPUCLK_RATE(1464000000, 1, 5),
PX30_CPUCLK_RATE(1440000000, 1, 5),
PX30_CPUCLK_RATE(1416000000, 1, 5),
PX30_CPUCLK_RATE(1392000000, 1, 5),
PX30_CPUCLK_RATE(1368000000, 1, 5),
PX30_CPUCLK_RATE(1344000000, 1, 5),
PX30_CPUCLK_RATE(1320000000, 1, 5),
PX30_CPUCLK_RATE(1296000000, 1, 5),
PX30_CPUCLK_RATE(1272000000, 1, 5),
PX30_CPUCLK_RATE(1248000000, 1, 5),
PX30_CPUCLK_RATE(1224000000, 1, 5),
PX30_CPUCLK_RATE(1200000000, 1, 5),
PX30_CPUCLK_RATE(1104000000, 1, 5),
PX30_CPUCLK_RATE(1008000000, 1, 5),