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FROMLIST: arm64: Add support for trace synchronization barrier

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tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.

Bug: 174685394
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/linux-arm-kernel/20210225193543.2920532-7-suzuki.poulose@arm.com/
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I36f91c3d9d2b1abeeabcb2c4f05e9eccaefae8ac
This commit is contained in:
Suzuki K Poulose
2021-02-24 23:58:44 +00:00
committed by Todd Kjos
parent 74f5800ef9
commit 3089a1c496
1 changed files with 1 additions and 0 deletions
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arch/arm64/include/asm/barrier.h
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@@ -23,6 +23,7 @@
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define psb_csync() asm volatile("hint #17" : : : "memory")
#define tsb_csync() asm volatile("hint #18" : : : "memory")
#define csdb() asm volatile("hint #20" : : : "memory")
#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \