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pwm: rockchip: Add comments for why to add delay before disabling the dclk for PWM v4

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Fixes: 42e759004f ("pwm: rockchip: add one period delay before disabling the dclk")
Change-Id: I612fde2adf60940e17146a115a104caf302109b2
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2025-07-01 17:34:42 +08:00
committed by Tao Huang
parent 77234413d3
commit 3192296029
1 changed files with 5 additions and 0 deletions
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5
drivers/pwm/pwm-rockchip.c
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@@ -873,6 +873,11 @@ static int rockchip_pwm_enable_v4(struct pwm_chip *chip, struct pwm_device *pwm,
writel_relaxed(PWM_EN(enable) | PWM_CLK_EN(enable), pc->base + ENABLE);
/*
* For pwm v4, the disable operation, which sets polarity to inactive state,
* will not take effect until the end of current period. Therefore, it makes
* sense to delay one period before disabling the dclk.
*/
if (!enable) {
pwm_get_state(pwm, &curstate);
delay_us = DIV_ROUND_UP_ULL(curstate.period, NSEC_PER_USEC);