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UPSTREAM: arm: dts: rockchip: add reset node for the exist saradc SoCs

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SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Change-Id: Iaafd41b163ebd853278baea5c1c10dc82c54792b
 (cherry picked from commit 3d4267a5a3)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This commit is contained in:
Jacob Chen
2016-12-09 14:40:18 +08:00
committed by Huang, Tao
parent 5c2eebd931
commit 31c917aebe
2 changed files with 4 additions and 0 deletions
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2
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -283,6 +283,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};

2
arch/arm/boot/dts/rk3xxx.dtsi
View File

@@ -409,6 +409,8 @@
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};