shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

Merge commit 'ab55f1c685dfe496d7b10e559877c2eaf29db8cb'

Browse Source 
* commit 'ab55f1c685dfe496d7b10e559877c2eaf29db8cb': (34 commits)
  media: rockchip: isp: support 8k for isp32 lite
  media: rockchip: isp: fix isp32 lite frame buffer data read
  media: rockchip: isp: add ioctl to get bay3d buf
  arm64: dts: rockchip: rk3588-amp: add configs for amp irqs
  arm64: dts: rockchip: rk3568-amp: add configs for amp irqs
  soc: rockchip: power-domain: Add pd status module param for debug
  video: rockchip: mpp: rkvenc2: Fix rw_sem error
  arm64: dts: rockchip: rk3588-vehicle-evb: maxim support 1080p display
  arm64: dts: rockchip: rk3588-vehicle-evb-v21/v22: Use vehicle dummy driver for gear selection
  ASoC: rockchip: rk817-codec: fix pop from DAC_DIG_CLK_DIS and DAC_DIG_CLK_EN
  misc: rk628: bt1120: add yc-swap and uv-swap property
  arm64: dts: rockchip: rk3588-evb: rk628 change the interrupt to rise edge trigger
  misc: rk628: bt1120-2-hdmi: set bus_format for bt1120
  media: i2c: add sc3336p sensor driver
  media: i2c: lt8668sx: fix kernel-6.1 compile errors
  dt-bindings: soc: rockchip-amp: remove CPU_GET_AFFINITY() to dtsi file
  ARM: dts: rockchip: add rv1106g-evb2-v12-spi-nand-tb.dts
  arm64: dts: rockchip: rk3562-amp: define CPU_GET_AFFINITY
  arm64: dts: rockchip: rk3308-amp: define CPU_GET_AFFINITY
  soc: rockchip: amp: support init gpio group irqs for amp
  ...

Change-Id: I1820698562bf7bbf368136fb222af72c9c23b16c

Conflicts:
	drivers/irqchip/irq-gic-v3.c
This commit is contained in:
Tao Huang
2024-02-29 19:30:20 +08:00
parent a921ab6d72 ab55f1c685
commit 3399e1b989
65 changed files with 3769 additions and 998 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@@ -1162,6 +1162,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1106g-evb2-v12-nofastae-emmc.dtb \
rv1106g-evb2-v12-nofastae-spi-nand.dtb \
rv1106g-evb2-v12-nofastae-spi-nor.dtb \
rv1106g-evb2-v12-spi-nand-tb.dtb \
rv1106g-evb2-v12-wakeup.dtb \
rv1106g-smart-door-lock-rmsl-v10.dtb \
rv1106g-smart-door-lock-rmsl-v12.dtb \

56
arch/arm/boot/dts/rv1106-evb-dual-cam.dtsi
View File

@@ -44,6 +44,12 @@
remote-endpoint = <&sc301iot_out>;
data-lanes = <1 2>;
};
csi_dphy_input6: endpoint@4 {
reg = <4>;
remote-endpoint = <&sc530ai_out>;
data-lanes = <1 2>;
};
};
port@1 {
@@ -88,6 +94,12 @@
remote-endpoint = <&sc301iot_1_out>;
data-lanes = <1 2>;
};
csi_dphy_input7: endpoint@4 {
reg = <4>;
remote-endpoint = <&sc530ai_1_out>;
data-lanes = <1 2>;
};
};
port@1 {
@@ -175,6 +187,28 @@
};
};
sc530ai: sc530ai@30 {
compatible = "smartsens,sc530ai";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2115-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc530ai_out: endpoint {
remote-endpoint = <&csi_dphy_input6>;
data-lanes = <1 2>;
};
};
};
sc4336: sc4336@30 {
compatible = "smartsens,sc4336";
status = "okay";
@@ -240,6 +274,28 @@
};
};
};
sc530ai_1: sc530ai_1@32 {
compatible = "smartsens,sc530ai";
status = "okay";
reg = <0x32>;
clocks = <&cru MCLK_REF_MIPI1>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out1>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2115-PC1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc530ai_1_out: endpoint {
remote-endpoint = <&csi_dphy_input7>;
data-lanes = <1 2>;
};
};
};
};
&mipi0_csi2 {

40
arch/arm/boot/dts/rv1106g-evb2-v12-spi-nand-tb.dts Normal file
View File

@@ -0,0 +1,40 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106g-evb2-v10.dts"
/ {
model = "Rockchip RV1106G EVB2 V12 Board On Spi Nand";
compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
};
/delete-node/ &thunder_boot_spi_nor;
&emmc {
status = "disabled";
};
&rkisp_thunderboot {
/* reg's offset MUST match with RTOS */
/*
* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
* e.g. 2304x1296: 0xf30000
*/
reg = <0x00860000 0xf30000>;
};
&ramdisk_r {
reg = <0x1790000 (20 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x2b90000 (10 * 0x00100000)>;
};

46
arch/arm/mach-rockchip/rv1106_pm.c
View File

@@ -27,6 +27,24 @@
#define RV1106_PM_REG_REGION_MEM_SIZE SZ_4K
#define CRU_PVTPLL0_CON0_L 0x00
#define CRU_PVTPLL0_CON0_H 0x04
#define CRU_PVTPLL0_CON1_L 0x08
#define CRU_PVTPLL0_CON1_H 0x0c
#define CRU_PVTPLL0_CON2_L 0x10
#define CRU_PVTPLL0_CON2_H 0x14
#define CRU_PVTPLL0_CON3_L 0x18
#define CRU_PVTPLL0_CON3_H 0x1c
#define CRU_PVTPLL1_CON0_L 0x30
#define CRU_PVTPLL1_CON0_H 0x34
#define CRU_PVTPLL1_CON1_L 0x38
#define CRU_PVTPLL1_CON1_H 0x3c
#define CRU_PVTPLL1_CON2_L 0x40
#define CRU_PVTPLL1_CON2_H 0x44
#define CRU_PVTPLL1_CON3_L 0x48
#define CRU_PVTPLL1_CON3_H 0x4c
enum {
RV1106_GPIO_PULL_NONE,
RV1106_GPIO_PULL_UP,
@@ -114,10 +132,6 @@ static struct reg_region vd_core_reg_rgns[] = {
{ REG_REGION(0x300, 0x310, 4, &corecru_base, WMSK_VAL)},
{ REG_REGION(0x800, 0x804, 4, &corecru_base, WMSK_VAL)},
/* pvtpll_cru */
{ REG_REGION(0x00, 0x24, 4, &pvtpllcru_base, WMSK_VAL)},
{ REG_REGION(0x30, 0x54, 4, &pvtpllcru_base, WMSK_VAL)},
/* core_sgrf */
{ REG_REGION(0x004, 0x014, 4, &coresgrf_base, 0)},
{ REG_REGION(0x000, 0x000, 4, &coresgrf_base, 0)},
@@ -1028,6 +1042,28 @@ static void gpio_restore(void)
static struct uart_debug_ctx debug_port_save;
static u32 cru_mode;
static u32 pvtpll0_length, pvtpll1_length;
static void pvtpllcru_save(void)
{
pvtpll0_length = readl_relaxed(pvtpllcru_base + CRU_PVTPLL0_CON0_H);
pvtpll1_length = readl_relaxed(pvtpllcru_base + CRU_PVTPLL1_CON0_H);
}
static void pvtpllcru_restore(void)
{
writel_relaxed(0x00030000, pvtpllcru_base + CRU_PVTPLL0_CON0_L);
writel_relaxed(0x007f0000 | pvtpll0_length, pvtpllcru_base + CRU_PVTPLL0_CON0_H);
writel_relaxed(0xffff0018, pvtpllcru_base + CRU_PVTPLL0_CON1_L);
writel_relaxed(0xffff0004, pvtpllcru_base + CRU_PVTPLL0_CON2_H);
writel_relaxed(0x00030003, pvtpllcru_base + CRU_PVTPLL0_CON0_L);
writel_relaxed(0x00030000, pvtpllcru_base + CRU_PVTPLL1_CON0_L);
writel_relaxed(0x007f0000 | pvtpll1_length, pvtpllcru_base + CRU_PVTPLL1_CON0_H);
writel_relaxed(0xffff0018, pvtpllcru_base + CRU_PVTPLL1_CON1_L);
writel_relaxed(0xffff0004, pvtpllcru_base + CRU_PVTPLL1_CON2_H);
writel_relaxed(0x00030003, pvtpllcru_base + CRU_PVTPLL1_CON0_L);
}
static void vd_log_regs_save(void)
{
@@ -1038,6 +1074,7 @@ static void vd_log_regs_save(void)
gic400_save();
rkpm_printch('b');
pvtpllcru_save();
rkpm_reg_rgn_save(vd_core_reg_rgns, ARRAY_SIZE(vd_core_reg_rgns));
rkpm_printch('c');
rkpm_reg_rgn_save(vd_log_reg_rgns, ARRAY_SIZE(vd_log_reg_rgns));
@@ -1056,6 +1093,7 @@ static void vd_log_regs_restore(void)
rkpm_reg_rgn_restore(vd_core_reg_rgns, ARRAY_SIZE(vd_core_reg_rgns));
rkpm_reg_rgn_restore(vd_log_reg_rgns, ARRAY_SIZE(vd_log_reg_rgns));
pvtpllcru_restore();
/* wait lock */
pm_pll_wait_lock(RV1106_APLL_ID);

2
arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi
View File

@@ -5,6 +5,8 @@
#include <dt-bindings/soc/rockchip-amp.h>
#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 0 | ((cluster) << 8))
/ {
rockchip_amp: rockchip-amp {
compatible = "rockchip,amp";

2
arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
View File

@@ -5,6 +5,8 @@
#include <dt-bindings/soc/rockchip-amp.h>
#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 0 | ((cluster) << 8))
/ {
rockchip_amp: rockchip-amp {
compatible = "rockchip,amp";

115
arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi
View File

@@ -3,6 +3,22 @@
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/soc/rockchip-amp.h>
#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 8)
#define RSVD0_IRQn 283
#define RSVD_IRQn(_N) (RSVD0_IRQn + (_N))
#define AMP_CPUOFF_REQ_IRQ(cpu) RSVD_IRQn(11 + (cpu)) /* gic irq: 294 */
#define GIC_TOUCH_REQ_IRQ(cpu) (AMP_CPUOFF_REQ_IRQ(4) + cpu) /* gic irq: 298 */
#define GPIO_IRQ_GROUP_DISABLE 0x0
#define GPIO_IRQ_GROUP_EN_BANK_TYPE 0x1
#define GPIO_IRQ_GROUP_EN_GROUP_TYPE 0x2
#define GPIO4_IRQn 69
#define GPIO3_IRQn 68
#define GPIO2_IRQn 67
#define GPIO1_IRQn 66
#define GPIO0_IRQn 65
/ {
rockchip_amp: rockchip-amp {
compatible = "rockchip,rk3568-amp";
@@ -14,11 +30,108 @@
pinctrl-0 = <&uart4m1_xfer>;
status = "okay";
amp-irqs = /bits/ 64 <
GIC_AMP_IRQ_CFG_ROUTE(152, 0xd0, CPU_GET_AFFINITY(3, 0))
GIC_AMP_IRQ_CFG_ROUTE(AMP_CPUOFF_REQ_IRQ(3), 0xd0, CPU_GET_AFFINITY(3, 0))
GIC_AMP_IRQ_CFG_ROUTE(GIC_TOUCH_REQ_IRQ(3), 0xd0, CPU_GET_AFFINITY(3, 0))>;
gpio-group-banks = <5>;
gpio-group {
status = "disabled";
amp-gpio0 {
gpio-bank-id = <0>;
group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
bank-type-cfg {
hw-irq = <GPIO0_IRQn>;
hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
prio = <0xd0>;
status = "disabled";
};
};
amp-gpio1 {
gpio-bank-id = <1>;
group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
bank-type-cfg {
hw-irq = <GPIO1_IRQn>;
hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
prio = <0xd0>;
status = "disabled";
};
};
amp-gpio2 {
gpio-bank-id = <2>;
group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
bank-type-cfg {
hw-irq = <GPIO2_IRQn>;
hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
prio = <0xd0>;
status = "disabled";
};
};
amp-gpio3 {
gpio-bank-id = <3>;
group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
bank-type-cfg {
hw-irq = <GPIO3_IRQn>;
hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
prio = <0xd0>;
status = "disabled";
};
};
amp-gpio4 {
gpio-bank-id = <4>;
group-irq-en = <GPIO_IRQ_GROUP_EN_GROUP_TYPE>;
bank-type-cfg {
hw-irq = <GPIO4_IRQn>;
hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
prio = <0xd0>;
status = "disabled";
};
prio-group0 {
group-prio = <0x80>;
group-irq-id = <RSVD_IRQn(39) RSVD_IRQn(40)
RSVD_IRQn(41) GPIO4_IRQn>;
group-irq-aff = /bits/ 64 <CPU_GET_AFFINITY(0, 0)
CPU_GET_AFFINITY(1, 0)
CPU_GET_AFFINITY(2, 0)
CPU_GET_AFFINITY(3, 0)>;
group-irq-en = <0x1 0x1 0x1 0x1>;
status = "disabled";
};
prio-group1 {
group-prio = <0x90>;
group-irq-id = <RSVD_IRQn(42) RSVD_IRQn(43)
RSVD_IRQn(44) RSVD_IRQn(45)>;
group-irq-aff = /bits/ 64 <CPU_GET_AFFINITY(0, 0)
CPU_GET_AFFINITY(1, 0)
CPU_GET_AFFINITY(2, 0)
CPU_GET_AFFINITY(3, 0)>;
group-irq-en = <0x0 0x1 0x1 0x1>;
status = "disabled";
};
prio-group2 {
group-prio = <0xA0>;
group-irq-id = <RSVD_IRQn(46) RSVD_IRQn(47)
RSVD_IRQn(48) RSVD_IRQn(49)>;
group-irq-aff = /bits/ 64 <CPU_GET_AFFINITY(0, 0)
CPU_GET_AFFINITY(1, 0)
CPU_GET_AFFINITY(2, 0)
CPU_GET_AFFINITY(3, 0)>;
group-irq-en = <0x1 0x1 0x1 0x1>;
status = "disabled";
};
};
};
amp_cpus: amp-cpus {
amp-cpu3 {
id = <0x0 0x300>;
entry = <0x0 0x2800000>;
boot-on = <0>;
boot-on = <1>;
mode = <0>;
};
};

14
arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi
View File

@@ -5,6 +5,8 @@
#include <dt-bindings/soc/rockchip-amp.h>
#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 8)
/ {
rockchip_amp: rockchip-amp {
compatible = "rockchip,amp";
@@ -17,6 +19,18 @@
pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>;
amp-irqs = /bits/ 64 <
/* GPIO EXT */
GIC_AMP_IRQ_CFG_ROUTE(314, 0xd0, CPU_GET_AFFINITY(3, 0))
GIC_AMP_IRQ_CFG_ROUTE(315, 0xd0, CPU_GET_AFFINITY(3, 0))
GIC_AMP_IRQ_CFG_ROUTE(316, 0xd0, CPU_GET_AFFINITY(3, 0))
GIC_AMP_IRQ_CFG_ROUTE(317, 0xd0, CPU_GET_AFFINITY(3, 0))
GIC_AMP_IRQ_CFG_ROUTE(318, 0xd0, CPU_GET_AFFINITY(3, 0))
/* UART5 */
GIC_AMP_IRQ_CFG_ROUTE(368, 0xd0, CPU_GET_AFFINITY(3, 0))
/* MAILBOX */
GIC_AMP_IRQ_CFG_ROUTE(100, 0xd0, CPU_GET_AFFINITY(3, 0))>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts
View File

@@ -108,7 +108,7 @@
pinctrl-names = "default";
pinctrl-0 = <&rk628_pin_1>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PB1 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <RK_PB1 IRQ_TYPE_EDGE_RISING>;
enable-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
@@ -148,7 +148,7 @@
pinctrl-names = "default";
pinctrl-0 = <&rk628_pin>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <RK_PC4 IRQ_TYPE_EDGE_RISING>;
enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;

2
arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts
View File

@@ -78,7 +78,7 @@
pinctrl-names = "default";
pinctrl-0 = <&rk628_pin>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <RK_PB2 IRQ_TYPE_EDGE_RISING>;
enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>;

21
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts
View File

@@ -35,23 +35,12 @@
#sound-dai-cells = <1>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
reverse {
label = "GPIO Key Reverse";
linux,code = <KEY_CAMERA_DOWN>;
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
park {
label = "GPIO Key Park";
linux,code = <KEY_CAMERA>;
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
vehicle_dummy: vehicle_dummy {
status = "okay";
compatible = "rockchip,vehicle-dummy-gpio";
reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
};
};

21
arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
View File

@@ -299,23 +299,12 @@
#sound-dai-cells = <1>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
reverse {
label = "GPIO Key Reverse";
linux,code = <KEY_CAMERA_DOWN>;
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
park {
label = "GPIO Key Park";
linux,code = <KEY_CAMERA>;
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
vehicle_dummy: vehicle_dummy {
status = "okay";
compatible = "rockchip,vehicle-dummy-gpio";
reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
};
vcc3v3_pcie_wifi: vcc3v3-pcie-wifi {

78
arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi
View File

@@ -489,57 +489,57 @@
0322 0024
//Init Default
0326 00E4
//HSYNC_WIDTH_L
0385 0038
//VSYNC_WIDTH_L
0386 0008
//HSYNC_WIDTH_L HSYNC=32
0385 0020
//VSYNC_WIDTH_L VSYNC=2
0386 0002
//HSYNC_WIDTH_H/VSYNC_WIDTH_H
0387 0000
//VFP_L
//VFP_L VFP=200
03A5 00C8
//VBP_H
03A7 0000
//VFP_H/VBP_L
03A6 0020
//VRES_L
//VFP_H/VBP_L VBP=8
03A6 0008
//VRES_L VRES=0X02D0=720
03A8 00D0
//VRES_H
03A9 0002
//HFP_L
//HFP_L HFP=56
03AA 0038
//HBP_H
03AC 0002
//HFP_H/HBP_L
03AB 0000
//HRES_L
03AC 0003
//HFP_H/HBP_L(4bit) HBP=56
03AB 0008
//HRES_L HRES=0X0780=1920
03AD 0080
//HRES_H
03AE 0007
//Disable FIFO/DESKEW_EN
03A4 00C0
//HSYNC_WIDTH_L
0395 0038
//VSYNC_WIDTH_L
0396 0008
//HSYNC_WIDTH_L HSYNC=40
0395 0028
//VSYNC_WIDTH_L VSYNC=20
0396 0014
//HSYNC_WIDTH_H/VSYNC_WIDTH_H
0397 0000
//VFP_L
03B1 00C8
//VFP_L VFP=15
03B1 000F
//VBP_H
03B3 0000
//VFP_H/VBP_L
03B2 0020
//VRES_L
03B4 00D0
//VFP_H/VBP_L VBP=10
03B2 000A
//VRES_L VRES=0X0438=1080
03B4 0038
//VRES_H
03B5 0002
//HFP_L
03B6 0038
03B5 0004
//HFP_L HFP=140
03B6 008C
//HBP_H
03B8 0002
//HFP_H/HBP_L
03B7 0000
//HRES_L
03B8 0006
//HFP_H/HBP_L HBP=100
03B7 0004
//HRES_L HRES=0X0780=1920
03B9 0080
//HRES_H
03BA 0007
@@ -870,15 +870,15 @@
panel-size= <346 194>;
panel-timing {
clock-frequency = <115200000>;
clock-frequency = <148500000>;
hactive = <1920>;
vactive = <720>;
hfront-porch = <56>;
hsync-len = <32>;
hback-porch = <56>;
vfront-porch = <200>;
vsync-len = <2>;
vback-porch = <8>;
vactive = <1080>;
hfront-porch = <140>;
hsync-len = <40>;
hback-porch = <100>;
vfront-porch = <15>;
vsync-len = <20>;
vback-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
@@ -2434,5 +2434,5 @@
&vp3 {
assigned-clocks = <&cru DCLK_VOP3>;
assigned-clock-parents = <&cru PLL_V0PLL>;
assigned-clock-parents = <&cru PLL_GPLL>;
};

8
drivers/clk/rockchip/clk-rv1106.c
View File

@@ -1007,12 +1007,16 @@ static void _cru_pvtpll_calibrate(int count_offset, int length_offset, int targe
writel_relaxed(val, rv1106_cru_base + length_offset);
usleep_range(2000, 2100);
rate1 = readl_relaxed(rv1106_cru_base + count_offset);
if ((rate1 < target_rate) || (rate1 >= rate0))
if (rate1 < target_rate)
return;
if (abs(rate1 - target_rate) < (target_rate >> 5))
return;
step = rate0 - rate1;
if (rate1 < rate0)
step = rate0 - rate1;
else
step = 5;
step = max_t(unsigned int, step, 5);
delta = rate1 - target_rate;
length += delta / step;
val = HIWORD_UPDATE(length, PVTPLL_LENGTH_SEL_MASK, PVTPLL_LENGTH_SEL_SHIFT);

32
drivers/irqchip/irq-gic-v3.c
View File

@@ -34,6 +34,10 @@
#include "irq-gic-common.h"
#ifdef CONFIG_ROCKCHIP_AMP
#include <soc/rockchip/rockchip_amp.h>
#endif
#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
@@ -361,6 +365,10 @@ static void gic_poke_irq(struct irq_data *d, u32 offset)
static void gic_mask_irq(struct irq_data *d)
{
#ifdef CONFIG_ROCKCHIP_AMP
if (rockchip_amp_check_amp_irq(gic_irq(d)))
return;
#endif
gic_poke_irq(d, GICD_ICENABLER);
if (gic_irq_in_rdist(d))
gic_redist_wait_for_rwp();
@@ -385,6 +393,10 @@ static void gic_eoimode1_mask_irq(struct irq_data *d)
static void gic_unmask_irq(struct irq_data *d)
{
#ifdef CONFIG_ROCKCHIP_AMP
if (rockchip_amp_check_amp_irq(gic_irq(d)))
return;
#endif
gic_poke_irq(d, GICD_ISENABLER);
}
@@ -571,6 +583,10 @@ static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)
static void gic_eoi_irq(struct irq_data *d)
{
#ifdef CONFIG_ROCKCHIP_AMP
if (rockchip_amp_check_amp_irq(gic_irq(d)))
return;
#endif
write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
isb();
@@ -908,6 +924,15 @@ void gic_v3_dist_init(void)
*/
affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
for (i = 32; i < GIC_LINE_NR; i++) {
#ifdef CONFIG_ROCKCHIP_AMP
u64 affinity_amp;
if (rockchip_amp_need_init_amp_irq(i)) {
affinity_amp = rockchip_amp_get_irq_aff(i);
gic_write_irouter(affinity_amp, base + GICD_IROUTER + i * 8);
continue;
}
#endif
trace_android_vh_gic_v3_affinity_init(i, GICD_IROUTER, &affinity);
gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
}
@@ -1359,6 +1384,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
int enabled;
u64 val;
#ifdef CONFIG_ROCKCHIP_AMP
if (rockchip_amp_check_amp_irq(gic_irq(d)))
return -EINVAL;
#endif
if (force)
cpu = cpumask_first(mask_val);
else
@@ -1992,6 +2021,9 @@ static int __init gic_init_bases(void __iomem *dist_base,
gic_update_rdist_properties();
#ifdef CONFIG_ROCKCHIP_AMP
rockchip_amp_get_gic_info(GIC_LINE_NR, GIC_V3);
#endif
gic_v3_dist_init();
gic_v3_cpu_init();
gic_smp_init();

10
drivers/media/i2c/Kconfig
View File

@@ -1842,6 +1842,16 @@ config VIDEO_SC3336
This is a Video4Linux2 sensor driver for the SmartSens
SC3336 camera.
config VIDEO_SC3336P
tristate "SmartSens SC3336P sensor support"
depends on I2C && VIDEO_DEV
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the SmartSens
SC3336P camera.
config VIDEO_SC3338
tristate "SmartSens SC3338 sensor support"
depends on I2C && VIDEO_DEV

1
drivers/media/i2c/Makefile
View File

@@ -234,6 +234,7 @@ obj-$(CONFIG_VIDEO_SC2336) += sc2336.o
obj-$(CONFIG_VIDEO_SC2355) += sc2355.o
obj-$(CONFIG_VIDEO_SC301IOT) += sc301iot.o
obj-$(CONFIG_VIDEO_SC3336) += sc3336.o
obj-$(CONFIG_VIDEO_SC3336P) += sc3336p.o
obj-$(CONFIG_VIDEO_SC3338) += sc3338.o
obj-$(CONFIG_VIDEO_SC401AI) += sc401ai.o
obj-$(CONFIG_VIDEO_SC4210) += sc4210.o

30
drivers/media/i2c/lt8668sx.c
View File

@@ -107,7 +107,7 @@ static const s64 link_freq_cphy_rgb_menu_items[] = {
};
struct lt8668sx {
struct v4l2_fwnode_bus_mipi_csi2 bus;
struct v4l2_mbus_config_mipi_csi2 bus;
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_ctrl_handler hdl;
@@ -960,15 +960,9 @@ static int lt8668sx_g_mbus_config(struct v4l2_subdev *sd,
unsigned int pad, struct v4l2_mbus_config *cfg)
{
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
u32 lane_num = lt8668sx->bus_cfg.bus.mipi_csi2.num_data_lanes;
u32 val = 0;
val = 1 << (lane_num - 1) |
V4L2_MBUS_CSI2_CHANNEL_0 |
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
cfg->type = lt8668sx->bus_cfg.bus_type;
cfg->flags = val;
cfg->bus.mipi_csi2 = lt8668sx->bus_cfg.bus.mipi_csi2;
return 0;
}
@@ -993,7 +987,7 @@ static int lt8668sx_s_stream(struct v4l2_subdev *sd, int on)
}
static int lt8668sx_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
@@ -1011,7 +1005,7 @@ static int lt8668sx_enum_mbus_code(struct v4l2_subdev *sd,
}
static int lt8668sx_enum_frame_sizes(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
@@ -1031,7 +1025,7 @@ static int lt8668sx_enum_frame_sizes(struct v4l2_subdev *sd,
}
static int lt8668sx_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *format)
{
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
@@ -1066,7 +1060,7 @@ static int lt8668sx_get_fmt(struct v4l2_subdev *sd,
}
static int lt8668sx_enum_frame_interval(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_interval_enum *fie)
{
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
@@ -1084,7 +1078,7 @@ static int lt8668sx_enum_frame_interval(struct v4l2_subdev *sd,
}
static int lt8668sx_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *format)
{
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
@@ -1092,7 +1086,7 @@ static int lt8668sx_set_fmt(struct v4l2_subdev *sd,
/* is overwritten by get_fmt */
u32 code = format->format.code;
int ret = lt8668sx_get_fmt(sd, cfg, format);
int ret = lt8668sx_get_fmt(sd, sd_state, format);
format->format.code = code;
@@ -1279,7 +1273,7 @@ static int lt8668sx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
struct v4l2_mbus_framefmt *try_fmt =
v4l2_subdev_get_try_format(sd, fh->pad, 0);
v4l2_subdev_get_try_format(sd, fh->state, 0);
const struct lt8668sx_mode *def_mode = &lt8668sx->support_modes[0];
mutex_lock(&lt8668sx->confctl_mutex);
@@ -1700,7 +1694,7 @@ static int lt8668sx_probe(struct i2c_client *client,
snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
lt8668sx->module_index, facing,
LT8668SX_NAME, dev_name(sd->dev));
err = v4l2_async_register_subdev_sensor_common(sd);
err = v4l2_async_register_subdev_sensor(sd);
if (err < 0) {
v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
goto err_clean_entity;
@@ -1735,7 +1729,7 @@ err_work_queues:
return err;
}
static int lt8668sx_remove(struct i2c_client *client)
static void lt8668sx_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct lt8668sx *lt8668sx = to_lt8668sx(sd);
@@ -1754,8 +1748,6 @@ static int lt8668sx_remove(struct i2c_client *client)
v4l2_ctrl_handler_free(&lt8668sx->hdl);
mutex_destroy(&lt8668sx->confctl_mutex);
clk_disable_unprepare(lt8668sx->xvclk);
return 0;
}
#if IS_ENABLED(CONFIG_OF)

1921
drivers/media/i2c/sc3336p.c Normal file
View File

File diff suppressed because it is too large Load Diff

43
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -669,6 +669,19 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
return -EINVAL;
}
if ((dev->unite_div == ISP_UNITE_DIV4 ||
(dev->isp_ver == ISP_V32_L &&
stream->id == RKISP_STREAM_SP &&
dev->unite_div == ISP_UNITE_DIV2)) &&
(pixm->width != dev->isp_sdev.out_crop.width ||
pixm->height != dev->isp_sdev.out_crop.height)) {
pixm->width = dev->isp_sdev.out_crop.width;
pixm->height = dev->isp_sdev.out_crop.height;
v4l2_warn(&dev->v4l2_dev,
"%s no support scale force to %dx%d\n",
__func__, pixm->width, pixm->height);
}
/* do checks on resolution */
restrict_rsz_resolution(stream, config, &max_rsz);
if (stream->id == RKISP_STREAM_MP ||
@@ -1471,8 +1484,7 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
const struct v4l2_rect *in)
{
struct rkisp_device *dev = stream->ispdev;
bool is_unite = !!dev->hw_dev->unite;
u32 align = is_unite ? 4 : 2;
u32 align = (dev->unite_div > ISP_UNITE_DIV1) ? 4 : 2;
/* Not crop for MP bayer raw data and dmatx path */
if ((stream->id == RKISP_STREAM_MP &&
@@ -1492,6 +1504,7 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
sel->left = ALIGN(sel->left, 2);
sel->width = ALIGN(sel->width, align);
sel->height = ALIGN(sel->height, align);
sel->left = clamp_t(u32, sel->left, 0,
in->width - STREAM_MIN_MP_SP_INPUT_WIDTH);
sel->top = clamp_t(u32, sel->top, 0,
@@ -1500,11 +1513,19 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
in->width - sel->left);
sel->height = clamp_t(u32, sel->height, STREAM_MIN_MP_SP_INPUT_HEIGHT,
in->height - sel->top);
if (is_unite && (sel->width + 2 * sel->left) != in->width) {
if (dev->unite_div > ISP_UNITE_DIV1 &&
(sel->width + 2 * sel->left) != in->width) {
sel->left = ALIGN_DOWN((in->width - sel->width) / 2, 2);
v4l2_warn(&dev->v4l2_dev,
"try horizontal center crop(%d,%d)/%dx%d for dual isp\n",
sel->left, sel->top, sel->width, sel->height);
"try horizontal center left:%d width:%d for unite mode\n",
sel->left, sel->width);
}
if (dev->unite_div == ISP_UNITE_DIV4 &&
(sel->height + 2 * sel->top) != in->height) {
sel->top = ALIGN_DOWN((in->height - sel->height) / 2, 2);
v4l2_warn(&dev->v4l2_dev,
"try vertical center top:%d height:%d for unite mode\n",
sel->top, sel->height);
}
stream->is_crop_upd = true;
return sel;
@@ -1764,11 +1785,15 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev)
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
ret = rkisp_register_stream_v32(dev);
} else if (dev->isp_ver == ISP_V32_L) {
st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L;
st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L;
st_cfg->max_rsz_width = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_L_UNITE : CIF_ISP_INPUT_W_MAX_V32_L;
st_cfg->max_rsz_height = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
st_cfg = &rkisp_sp_stream_config;
st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L;
st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32_L;
st_cfg->max_rsz_width = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_L_UNITE : CIF_ISP_INPUT_W_MAX_V32_L;
st_cfg->max_rsz_height = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
ret = rkisp_register_stream_v32(dev);
}

18
drivers/media/platform/rockchip/isp/capture_v30.c
View File

@@ -635,7 +635,8 @@ static int fbc_config_mi(struct rkisp_stream *stream)
u32 left_w = (stream->out_fmt.width / 2) & ~0xf;
offs += left_w * mult;
rkisp_next_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false);
rkisp_idx_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET,
offs, ISP_UNITE_RIGHT, false);
}
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0,
CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN, false);
@@ -784,18 +785,18 @@ static void update_mi(struct rkisp_stream *stream)
reg = stream->config->mi.y_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
val += ((stream->out_fmt.width / div) & ~0xf);
rkisp_next_write(dev, reg, val, false);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
reg = stream->config->mi.cb_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
val += ((stream->out_fmt.width / div) & ~0xf) * mult;
rkisp_next_write(dev, reg, val, false);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP) {
reg = stream->config->mi.cr_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
val += ((stream->out_fmt.width / div) & ~0xf);
rkisp_next_write(dev, reg, val, false);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
}
}
@@ -836,9 +837,12 @@ static void update_mi(struct rkisp_stream *stream)
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"%s stream:%d Y:0x%x CB:0x%x | Y_SHD:0x%x, right\n",
__func__, stream->id,
rkisp_next_read(dev, stream->config->mi.y_base_ad_init, false),
rkisp_next_read(dev, stream->config->mi.cb_base_ad_init, false),
rkisp_next_read(dev, stream->config->mi.y_base_ad_shd, true));
rkisp_idx_read(dev, stream->config->mi.y_base_ad_init,
ISP_UNITE_RIGHT, false),
rkisp_idx_read(dev, stream->config->mi.cb_base_ad_init,
ISP_UNITE_RIGHT, false),
rkisp_idx_read(dev, stream->config->mi.y_base_ad_shd,
ISP_UNITE_RIGHT, true));
}
static struct streams_ops rkisp_mp_streams_ops = {

77
drivers/media/platform/rockchip/isp/capture_v32.c
View File

@@ -752,8 +752,7 @@ static int mp_config_mi(struct rkisp_stream *stream)
mi_frame_end_int_enable(stream);
/* set up first buffer */
if (!dev->cap_dev.wrap_line || stream->dummy_buf.mem_priv)
mi_frame_end(stream, FRAME_INIT);
mi_frame_end(stream, FRAME_INIT);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
@@ -1026,6 +1025,8 @@ static void update_mi(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
struct rkisp_dummy_buffer *dummy_buf = &stream->dummy_buf;
struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2;
u32 val, reg;
bool is_cr_cfg = false;
@@ -1049,22 +1050,63 @@ static void update_mi(struct rkisp_stream *stream)
rkisp_write(dev, reg, val, false);
}
if (dev->hw_dev->unite) {
if (dev->unite_div > ISP_UNITE_DIV1) {
/* right of image, or right top of image */
reg = stream->config->mi.y_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
val += ((stream->out_fmt.width / 2) & ~0xf);
rkisp_next_write(dev, reg, val, false);
val += ((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
reg = stream->config->mi.cb_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
val += ((stream->out_fmt.width / 2) & ~0xf);
rkisp_next_write(dev, reg, val, false);
val += ((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
if (is_cr_cfg) {
reg = stream->config->mi.cr_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
val += ((stream->out_fmt.width / 2) & ~0xf);
rkisp_next_write(dev, reg, val, false);
val += ((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
}
}
if (dev->unite_div == ISP_UNITE_DIV4) {
/* left bottom of image */
reg = stream->config->mi.y_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
val += (out_fmt->plane_fmt[0].bytesperline * out_fmt->height / 2);
rkisp_idx_write(dev, reg, val, ISP_UNITE_LEFT_B, false);
reg = stream->config->mi.cb_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
val += (out_fmt->plane_fmt[1].sizeimage / 2);
rkisp_idx_write(dev, reg, val, ISP_UNITE_LEFT_B, false);
if (is_cr_cfg) {
reg = stream->config->mi.cr_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
val += (out_fmt->plane_fmt[2].sizeimage / 2);
rkisp_idx_write(dev, reg, val, ISP_UNITE_LEFT_B, false);
}
/* right bottom of image */
reg = stream->config->mi.y_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
val += (out_fmt->plane_fmt[0].bytesperline * out_fmt->height / 2) +
((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT_B, false);
reg = stream->config->mi.cb_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
val += (out_fmt->plane_fmt[1].sizeimage / 2) +
((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT_B, false);
if (is_cr_cfg) {
reg = stream->config->mi.cr_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
val += (out_fmt->plane_fmt[2].sizeimage / 2) +
((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT_B, false);
}
}
@@ -1112,15 +1154,15 @@ static void update_mi(struct rkisp_stream *stream)
} else if (dummy_buf->mem_priv) {
val = dummy_buf->dma_addr;
reg = stream->config->mi.y_base_ad_init;
rkisp_write(dev, reg, val, false);
rkisp_unite_write(dev, reg, val, false);
/* wrap buf ENC */
if (dev->isp_ver == ISP_V32)
val += stream->out_fmt.plane_fmt[0].bytesperline * dev->cap_dev.wrap_line;
reg = stream->config->mi.cb_base_ad_init;
rkisp_write(dev, reg, val, false);
rkisp_unite_write(dev, reg, val, false);
if (is_cr_cfg) {
reg = stream->config->mi.cr_base_ad_init;
rkisp_write(dev, reg, val, false);
rkisp_unite_write(dev, reg, val, false);
}
} else if (stream->is_using_resmem) {
/* resmem for fast stream NV12 output */
@@ -1139,7 +1181,7 @@ static void update_mi(struct rkisp_stream *stream)
/* no next buf to preclose mi */
stream->ops->disable_mi(stream);
/* no buf, force to close mi */
if (!stream->curr_buf)
if (!stream->curr_buf && dev->hw_dev->is_single)
stream_self_update(stream);
}
@@ -1422,7 +1464,10 @@ static int mi_frame_end(struct rkisp_stream *stream, u32 state)
struct rkisp_buffer *buf = NULL;
u32 i;
if (stream->id == RKISP_STREAM_VIR)
/* STREAM_VIR or STREAM_MP wrap buf from rockit */
if (stream->id == RKISP_STREAM_VIR ||
(stream->id == RKISP_STREAM_MP && dev->cap_dev.wrap_line &&
!stream->dummy_buf.mem_priv && stream->dummy_buf.dma_addr))
return 0;
if (dev->cap_dev.is_done_early &&
@@ -2302,8 +2347,8 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev)
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
"mi isr:0x%x\n", mis_val);
if (dev->hw_dev->unite == ISP_UNITE_ONE &&
dev->unite_index == ISP_UNITE_LEFT) {
if ((dev->unite_div == ISP_UNITE_DIV2 && dev->unite_index != ISP_UNITE_RIGHT) ||
(dev->unite_div == ISP_UNITE_DIV4 && dev->unite_index != ISP_UNITE_RIGHT_B)) {
rkisp_write(dev, ISP3X_MI_ICR, mis_val, true);
goto end;
}

145
drivers/media/platform/rockchip/isp/common.c
View File

@@ -27,19 +27,31 @@ void rkisp_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
}
}
void rkisp_next_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
void rkisp_idx_write(struct rkisp_device *dev, u32 reg, u32 val, int idx, bool is_direct)
{
u32 offset = RKISP_ISP_SW_MAX_SIZE + reg;
u32 *mem = dev->sw_base_addr + offset;
u32 *flag = dev->sw_base_addr + offset + RKISP_ISP_SW_REG_SIZE;
struct rkisp_hw_dev *hw = dev->hw_dev;
void __iomem *base_addr = hw->base_addr;
u32 *mem, *flag, offset = idx * RKISP_ISP_SW_MAX_SIZE;
if (!hw->unite)
offset = 0;
/* right for isp1 hardware */
if (hw->unite == ISP_UNITE_TWO && (idx & 0x1))
base_addr = hw->base_next_addr;
mem = dev->sw_base_addr + reg + offset;
flag = dev->sw_base_addr + reg + RKISP_ISP_SW_REG_SIZE + offset;
*mem = val;
*flag = SW_REG_CACHE;
if (dev->hw_dev->is_single || is_direct) {
*flag = SW_REG_CACHE_SYNC;
if (dev->hw_dev->unite == ISP_UNITE_ONE)
return;
writel(val, dev->hw_dev->base_next_addr + reg);
if (dev->isp_ver == ISP_V32 && reg <= 0x200)
rv1106_sdmmc_get_lock();
if (idx == ISP_UNITE_LEFT ||
(hw->unite == ISP_UNITE_TWO && idx == ISP_UNITE_RIGHT))
writel(val, base_addr + reg);
if (dev->isp_ver == ISP_V32 && reg <= 0x200)
rv1106_sdmmc_put_lock();
}
}
@@ -54,14 +66,22 @@ u32 rkisp_read(struct rkisp_device *dev, u32 reg, bool is_direct)
return val;
}
u32 rkisp_next_read(struct rkisp_device *dev, u32 reg, bool is_direct)
u32 rkisp_idx_read(struct rkisp_device *dev, u32 reg, int idx, bool is_direct)
{
u32 val;
struct rkisp_hw_dev *hw = dev->hw_dev;
void __iomem *base_addr = hw->base_addr;
u32 val, offset = idx * RKISP_ISP_SW_MAX_SIZE;
if (dev->hw_dev->is_single || is_direct)
val = readl(dev->hw_dev->base_next_addr + reg);
if (!hw->unite)
offset = 0;
/* right for isp1 hardware */
if (hw->unite == ISP_UNITE_TWO && (idx & 0x1))
base_addr = hw->base_next_addr;
if (hw->is_single || is_direct)
val = readl(base_addr + reg);
else
val = *(u32 *)(dev->sw_base_addr + RKISP_ISP_SW_MAX_SIZE + reg);
val = *(u32 *)(dev->sw_base_addr + reg + offset);
return val;
}
@@ -72,11 +92,11 @@ void rkisp_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool i
rkisp_write(dev, reg, val | tmp, is_direct);
}
void rkisp_next_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct)
void rkisp_idx_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, int idx, bool is_direct)
{
u32 tmp = rkisp_next_read(dev, reg, is_direct) & ~mask;
u32 tmp = rkisp_idx_read(dev, reg, idx, is_direct) & ~mask;
rkisp_next_write(dev, reg, val | tmp, is_direct);
rkisp_idx_write(dev, reg, val | tmp, idx, is_direct);
}
void rkisp_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct)
@@ -86,11 +106,11 @@ void rkisp_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direc
rkisp_write(dev, reg, tmp & ~mask, is_direct);
}
void rkisp_next_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct)
void rkisp_idx_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, int idx, bool is_direct)
{
u32 tmp = rkisp_next_read(dev, reg, is_direct);
u32 tmp = rkisp_idx_read(dev, reg, idx, is_direct);
rkisp_next_write(dev, reg, tmp & ~mask, is_direct);
rkisp_idx_write(dev, reg, tmp & ~mask, idx, is_direct);
}
void rkisp_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val)
@@ -100,11 +120,14 @@ void rkisp_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val)
*mem = val;
}
void rkisp_next_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val)
void rkisp_idx_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val, int idx)
{
u32 offset = RKISP_ISP_SW_MAX_SIZE + reg;
u32 *mem = dev->sw_base_addr + offset;
u32 offset = idx * RKISP_ISP_SW_MAX_SIZE;
u32 *mem;
if (!dev->hw_dev->unite)
offset = 0;
mem = dev->sw_base_addr + reg + offset;
*mem = val;
}
@@ -113,9 +136,13 @@ u32 rkisp_read_reg_cache(struct rkisp_device *dev, u32 reg)
return *(u32 *)(dev->sw_base_addr + reg);
}
u32 rkisp_next_read_reg_cache(struct rkisp_device *dev, u32 reg)
u32 rkisp_idx_read_reg_cache(struct rkisp_device *dev, u32 reg, int idx)
{
return *(u32 *)(dev->sw_base_addr + RKISP_ISP_SW_MAX_SIZE + reg);
u32 offset = idx * RKISP_ISP_SW_MAX_SIZE;
if (!dev->hw_dev->unite)
offset = 0;
return *(u32 *)(dev->sw_base_addr + reg + offset);
}
void rkisp_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val)
@@ -125,11 +152,11 @@ void rkisp_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 v
rkisp_write_reg_cache(dev, reg, val | tmp);
}
void rkisp_next_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val)
void rkisp_idx_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, int idx)
{
u32 tmp = rkisp_next_read_reg_cache(dev, reg) & ~mask;
u32 tmp = rkisp_idx_read_reg_cache(dev, reg, idx) & ~mask;
rkisp_next_write_reg_cache(dev, reg, val | tmp);
rkisp_idx_write_reg_cache(dev, reg, val | tmp, idx);
}
void rkisp_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask)
@@ -139,11 +166,11 @@ void rkisp_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask)
rkisp_write_reg_cache(dev, reg, tmp & ~mask);
}
void rkisp_next_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask)
void rkisp_idx_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, int idx)
{
u32 tmp = rkisp_next_read_reg_cache(dev, reg);
u32 tmp = rkisp_idx_read_reg_cache(dev, reg, idx);
rkisp_next_write_reg_cache(dev, reg, tmp & ~mask);
rkisp_idx_write_reg_cache(dev, reg, tmp & ~mask, idx);
}
void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
@@ -169,9 +196,9 @@ void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
continue;
}
if (hw->unite == ISP_UNITE_ONE && dev->unite_index == ISP_UNITE_RIGHT) {
val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
flag = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE + RKISP_ISP_SW_REG_SIZE;
if (hw->unite == ISP_UNITE_ONE && dev->unite_index > ISP_UNITE_LEFT) {
val += (RKISP_ISP_SW_MAX_SIZE * dev->unite_index / 4);
flag += (RKISP_ISP_SW_MAX_SIZE * dev->unite_index / 4);
}
if (*flag == SW_REG_CACHE) {
@@ -192,6 +219,42 @@ void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
}
}
int rkisp_buf_get_fd(struct rkisp_device *dev,
struct rkisp_dummy_buffer *buf, bool try_fd)
{
const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
bool new_dbuf = false;
if (!buf || !buf->mem_priv)
return -EINVAL;
if (try_fd && buf->is_need_dmafd)
return 0;
if (try_fd) {
buf->is_need_dbuf = true;
buf->is_need_dmafd = true;
}
if (buf->is_need_dbuf && !buf->dbuf) {
buf->dbuf = g_ops->get_dmabuf(&buf->vb, buf->mem_priv, O_RDWR);
new_dbuf = true;
}
if (buf->is_need_dmafd) {
buf->dma_fd = dma_buf_fd(buf->dbuf, O_CLOEXEC);
if (buf->dma_fd < 0) {
if (new_dbuf) {
dma_buf_put(buf->dbuf);
buf->dbuf = NULL;
buf->is_need_dbuf = false;
}
buf->is_need_dmafd = false;
return -EINVAL;
}
get_dma_buf(buf->dbuf);
}
return 0;
}
static void rkisp_init_dummy_vb2(struct rkisp_device *dev,
struct rkisp_dummy_buffer *buf)
{
@@ -240,17 +303,13 @@ int rkisp_alloc_buffer(struct rkisp_device *dev,
}
if (buf->is_need_vaddr)
buf->vaddr = g_ops->vaddr(&buf->vb, mem_priv);
if (buf->is_need_dbuf) {
buf->dbuf = g_ops->get_dmabuf(&buf->vb, mem_priv, O_RDWR);
if (buf->is_need_dmafd) {
buf->dma_fd = dma_buf_fd(buf->dbuf, O_CLOEXEC);
if (buf->dma_fd < 0) {
dma_buf_put(buf->dbuf);
ret = buf->dma_fd;
goto err;
}
get_dma_buf(buf->dbuf);
}
ret = rkisp_buf_get_fd(dev, buf, false);
if (ret < 0) {
g_ops->put(buf->mem_priv);
buf->mem_priv = NULL;
buf->vaddr = NULL;
buf->size = 0;
goto err;
}
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s buf:0x%x~0x%x size:%d\n", __func__,

19
drivers/media/platform/rockchip/isp/common.h
View File

@@ -176,19 +176,20 @@ u32 rkisp_read_reg_cache(struct rkisp_device *dev, u32 reg);
void rkisp_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val);
void rkisp_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask);
/* for dual isp, config for next isp reg */
void rkisp_next_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct);
u32 rkisp_next_read(struct rkisp_device *dev, u32 reg, bool is_direct);
void rkisp_next_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct);
void rkisp_next_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct);
/* for unite mode, config for diff isp reg */
void rkisp_idx_write(struct rkisp_device *dev, u32 reg, u32 val, int idx, bool is_direct);
u32 rkisp_idx_read(struct rkisp_device *dev, u32 reg, int idx, bool is_direct);
void rkisp_idx_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, int idx, bool is_direct);
void rkisp_idx_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, int idx, bool is_direct);
void rkisp_next_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val);
u32 rkisp_next_read_reg_cache(struct rkisp_device *dev, u32 reg);
void rkisp_next_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val);
void rkisp_next_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask);
void rkisp_idx_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val, int idx);
u32 rkisp_idx_read_reg_cache(struct rkisp_device *dev, u32 reg, int idx);
void rkisp_idx_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, int idx);
void rkisp_idx_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, int idx);
void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end);
int rkisp_buf_get_fd(struct rkisp_device *dev, struct rkisp_dummy_buffer *buf, bool try_fd);
int rkisp_alloc_buffer(struct rkisp_device *dev, struct rkisp_dummy_buffer *buf);
void rkisp_free_buffer(struct rkisp_device *dev, struct rkisp_dummy_buffer *buf);
void rkisp_prepare_buffer(struct rkisp_device *dev, struct rkisp_dummy_buffer *buf);

10
drivers/media/platform/rockchip/isp/dev.c
View File

@@ -183,7 +183,7 @@ static int __isp_pipeline_s_isp_clk(struct rkisp_pipeline *p)
struct v4l2_subdev *sd;
struct v4l2_ctrl *ctrl;
u64 data_rate = 0;
int i, fps;
int i, fps, size;
hw_dev->isp_size[dev->dev_id].is_on = true;
if (hw_dev->is_runing) {
@@ -200,14 +200,16 @@ static int __isp_pipeline_s_isp_clk(struct rkisp_pipeline *p)
fps = hw_dev->isp_size[i].fps;
if (!fps)
fps = 30;
data_rate += (fps * hw_dev->isp_size[i].size);
size = hw_dev->isp_size[i].size * hw_dev->isp[i]->unite_div;
data_rate += (fps * size);
}
} else {
i = dev->dev_id;
fps = hw_dev->isp_size[i].fps;
if (!fps)
fps = 30;
data_rate = fps * hw_dev->isp_size[i].size;
size = hw_dev->isp_size[i].size * dev->unite_div;
data_rate = fps * size;
}
goto end;
}
@@ -868,7 +870,7 @@ static int rkisp_plat_probe(struct platform_device *pdev)
return ret;
if (isp_dev->hw_dev->unite)
mult = 2;
mult = ISP_UNITE_MAX;
isp_dev->sw_base_addr = devm_kzalloc(dev, RKISP_ISP_SW_MAX_SIZE * mult, GFP_KERNEL);
if (!isp_dev->sw_base_addr)
return -ENOMEM;

41
drivers/media/platform/rockchip/isp/dev.h
View File

@@ -114,13 +114,24 @@ enum {
ISP_UNITE_ONE = 2,
};
/* left and right index
* ISP_UNITE_LEFT: left of image to isp process
* ISP_UNITE_RIGHT: right of image to isp process
/* image segmentation index
* ISP_UNITE_LEFT: left of image, or left top of image
* ISP_UNITE_RIGHT: right of image, or right top of image
* ISP_UNITE_LEFT_B: left bottom of image
* ISP_UNITE_RIGHT_B: right bottom of image
*/
enum {
ISP_UNITE_LEFT = 0,
ISP_UNITE_RIGHT = 1,
ISP_UNITE_RIGHT,
ISP_UNITE_LEFT_B,
ISP_UNITE_RIGHT_B,
ISP_UNITE_MAX,
};
enum {
ISP_UNITE_DIV1 = 1,
ISP_UNITE_DIV2 = 2,
ISP_UNITE_DIV4 = 4,
};
/*
@@ -286,32 +297,36 @@ struct rkisp_device {
u8 multi_index;
u8 rawaf_irq_cnt;
u8 unite_index;
u8 unite_div;
};
static inline void
rkisp_unite_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
{
rkisp_write(dev, reg, val, is_direct);
if (dev->hw_dev->unite)
rkisp_next_write(dev, reg, val, is_direct);
int i;
for (i = 0; i < dev->unite_div; i++)
rkisp_idx_write(dev, reg, val, i, is_direct);
}
static inline void
rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask,
u32 val, bool is_direct)
{
rkisp_set_bits(dev, reg, mask, val, is_direct);
if (dev->hw_dev->unite)
rkisp_next_set_bits(dev, reg, mask, val, is_direct);
int i;
for (i = 0; i < dev->unite_div; i++)
rkisp_idx_set_bits(dev, reg, mask, val, i, is_direct);
}
static inline void
rkisp_unite_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask,
bool is_direct)
{
rkisp_clear_bits(dev, reg, mask, is_direct);
if (dev->hw_dev->unite)
rkisp_next_clear_bits(dev, reg, mask, is_direct);
int i;
for (i = 0; i < dev->unite_div; i++)
rkisp_idx_clear_bits(dev, reg, mask, i, is_direct);
}
static inline bool rkisp_link_sensor(u32 isp_inp)

38
drivers/media/platform/rockchip/isp/dmarx.c
View File

@@ -364,6 +364,7 @@ static void update_rawrd(struct rkisp_stream *stream)
struct rkisp_device *dev = stream->ispdev;
void __iomem *base = dev->base_addr;
struct capture_fmt *fmt = &stream->out_isp_fmt;
u32 offs, offs_h = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
u32 val = 0;
if (stream->curr_buf) {
@@ -374,15 +375,22 @@ static void update_rawrd(struct rkisp_stream *stream)
}
val += stream->curr_buf->buff_addr[RKISP_PLANE_Y];
rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
if (dev->hw_dev->unite) {
u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
if (stream->memory)
offs *= DIV_ROUND_UP(fmt->bpp[0], 8);
else
offs = offs * fmt->bpp[0] / 8;
val += offs;
rkisp_next_write(dev, stream->config->mi.y_base_ad_init, val, false);
if (stream->memory)
offs_h *= DIV_ROUND_UP(fmt->bpp[0], 8);
else
offs_h = offs_h * fmt->bpp[0] / 8;
if (dev->unite_div > ISP_UNITE_DIV1)
rkisp_idx_write(dev, stream->config->mi.y_base_ad_init,
val + offs_h, ISP_UNITE_RIGHT, false);
if (dev->unite_div == ISP_UNITE_DIV4) {
offs = stream->out_fmt.plane_fmt[0].bytesperline *
(stream->out_fmt.height / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL);
rkisp_idx_write(dev, stream->config->mi.y_base_ad_init,
val + offs, ISP_UNITE_LEFT_B, false);
offs += offs_h;
rkisp_idx_write(dev, stream->config->mi.y_base_ad_init,
val + offs, ISP_UNITE_RIGHT_B, false);
}
stream->frame_end = false;
if (stream->id == RKISP_STREAM_RAWRD2 && stream->out_isp_fmt.fmt_type == FMT_YUV) {
@@ -1130,21 +1138,27 @@ void rkisp_rawrd_set_pic_size(struct rkisp_device *dev,
{
struct rkisp_isp_subdev *sdev = &dev->isp_sdev;
u8 mult = sdev->in_fmt.fmt_type == FMT_YUV ? 2 : 1;
bool is_unite = !!dev->hw_dev->unite;
u32 w = !is_unite ? width : width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
u32 w, h;
/* rx height should equal to isp height + offset for read back mode */
height = sdev->in_crop.top + sdev->in_crop.height;
w = width;
h = height;
if (dev->unite_div > ISP_UNITE_DIV1)
w = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (dev->unite_div == ISP_UNITE_DIV4)
h = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
/* isp20 extend line for normal read back mode to fix internal bug */
if (dev->isp_ver == ISP_V20 &&
sdev->in_fmt.fmt_type == FMT_BAYER &&
sdev->out_fmt.fmt_type != FMT_BAYER &&
dev->rd_mode == HDR_RDBK_FRAME1)
height += RKMODULE_EXTEND_LINE;
h += RKMODULE_EXTEND_LINE;
w *= mult;
rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, height << 16 | w, false);
rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, h << 16 | w, false);
}
void rkisp_dmarx_get_frame(struct rkisp_device *dev, u32 *id,

12
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -111,7 +111,7 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
};
u32 i, *flag, *reg, size;
u32 i, j, *flag, *reg, size;
switch (dev->isp_ver) {
case ISP_V20:
@@ -138,7 +138,7 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
for (i = 0; i < size; i++) {
flag = dev->sw_base_addr + reg[i] + RKISP_ISP_SW_REG_SIZE;
*flag = SW_REG_CACHE;
if (dev->hw_dev->unite) {
for (j = 1; j < ISP_UNITE_MAX && dev->hw_dev->unite; j++) {
flag += RKISP_ISP_SW_MAX_SIZE / 4;
*flag = SW_REG_CACHE;
}
@@ -1265,8 +1265,10 @@ void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev)
hw_dev->is_single = false;
w = isp->isp_sdev.in_crop.width;
h = isp->isp_sdev.in_crop.height;
if (hw_dev->unite)
if (isp->unite_div > ISP_UNITE_DIV1)
w = w / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (isp->unite_div == ISP_UNITE_DIV4)
h = h / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
hw_dev->isp_size[i].w = w;
hw_dev->isp_size[i].h = h;
hw_dev->isp_size[i].size = w * h;
@@ -1293,7 +1295,7 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
void __iomem *base = hw_dev->base_addr;
struct rkisp_device *isp;
int mult = hw_dev->unite ? 2 : 1;
int ret, i;
int ret, i, j;
void *buf;
ret = pinctrl_pm_select_default_state(dev);
@@ -1316,7 +1318,7 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
buf = isp->sw_base_addr;
memset(buf, 0, RKISP_ISP_SW_MAX_SIZE * mult);
memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
if (hw_dev->unite) {
for (j = 1; j < ISP_UNITE_MAX && hw_dev->unite; j++) {
buf += RKISP_ISP_SW_MAX_SIZE;
base = hw_dev->base_next_addr;
memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);

17
drivers/media/platform/rockchip/isp/isp_params.c
View File

@@ -46,8 +46,7 @@ static int rkisp_params_g_fmt_meta_out(struct file *file, void *fh,
memset(meta, 0, sizeof(*meta));
meta->dataformat = params_vdev->vdev_fmt.fmt.meta.dataformat;
meta->buffersize = params_vdev->vdev_fmt.fmt.meta.buffersize;
params_vdev->ops->get_param_size(params_vdev, &meta->buffersize);
return 0;
}
@@ -349,11 +348,7 @@ static int rkisp_init_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
else
ret = rkisp_init_params_vdev_v32(params_vdev);
params_vdev->vdev_fmt.fmt.meta.dataformat =
V4L2_META_FMT_RK_ISP1_PARAMS;
if (params_vdev->ops && params_vdev->ops->get_param_size)
params_vdev->ops->get_param_size(params_vdev,
&params_vdev->vdev_fmt.fmt.meta.buffersize);
params_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_PARAMS;
return ret;
}
@@ -487,6 +482,14 @@ int rkisp_params_info2ddr_cfg(struct rkisp_isp_params_vdev *params_vdev,
return ret;
}
void rkisp_params_get_bay3d_buffd(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_bay3dbuf_info *bay3dbuf)
{
memset(bay3dbuf, -1, sizeof(*bay3dbuf));
if (params_vdev->ops->get_bay3d_buffd)
params_vdev->ops->get_bay3d_buffd(params_vdev, bay3dbuf);
}
int rkisp_register_params_vdev(struct rkisp_isp_params_vdev *params_vdev,
struct v4l2_device *v4l2_dev,
struct rkisp_device *dev)

4
drivers/media/platform/rockchip/isp/isp_params.h
View File

@@ -42,6 +42,8 @@ struct rkisp_isp_params_ops {
void (*fop_release)(struct rkisp_isp_params_vdev *params_vdev);
bool (*check_bigmode)(struct rkisp_isp_params_vdev *params_vdev);
int (*info2ddr_cfg)(struct rkisp_isp_params_vdev *params_vdev, void *arg);
void (*get_bay3d_buffd)(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_bay3dbuf_info *bay3dbuf);
};
/*
@@ -147,4 +149,6 @@ void rkisp_params_meshbuf_free(struct rkisp_isp_params_vdev *params_vdev, u64 id
void rkisp_params_stream_stop(struct rkisp_isp_params_vdev *params_vdev);
bool rkisp_params_check_bigmode(struct rkisp_isp_params_vdev *params_vdev);
int rkisp_params_info2ddr_cfg(struct rkisp_isp_params_vdev *params_vdev, void *arg);
void rkisp_params_get_bay3d_buffd(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_bay3dbuf_info *bay3dbuf);
#endif /* _RKISP_ISP_PARAM_H */

1
drivers/media/platform/rockchip/isp/isp_params_v1x.c
View File

@@ -2239,6 +2239,7 @@ static void
rkisp1_get_param_size_v1x(struct rkisp_isp_params_vdev *params_vdev, unsigned int sizes[])
{
sizes[0] = sizeof(struct rkisp1_isp_params_cfg);
params_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
/* Not called when the camera active, thus not isr protection. */

22
drivers/media/platform/rockchip/isp/isp_params_v21.c
View File

@@ -3973,6 +3973,19 @@ end:
return ispdev->is_bigmode = is_bigmode;
}
static void
rkisp_params_get_bay3d_buffd_v21(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_bay3dbuf_info *bay3dbuf)
{
struct rkisp_isp_params_val_v21 *priv_val = params_vdev->priv_val;
struct rkisp_dummy_buffer *buf = &priv_val->buf_3dnr;
if (rkisp_buf_get_fd(params_vdev->dev, buf, true) < 0)
return;
bay3dbuf->iir_fd = buf->dma_fd;
bay3dbuf->iir_size = buf->size;
}
/* Not called when the camera active, thus not isr protection. */
static void
rkisp_params_first_cfg_v2x(struct rkisp_isp_params_vdev *params_vdev)
@@ -4092,6 +4105,7 @@ rkisp_get_param_size_v2x(struct rkisp_isp_params_vdev *params_vdev,
unsigned int sizes[])
{
sizes[0] = sizeof(struct isp2x_isp_params_cfg);
params_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static void
@@ -4330,19 +4344,23 @@ static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
.stream_stop = rkisp_params_stream_stop_v2x,
.fop_release = rkisp_params_fop_release_v2x,
.check_bigmode = rkisp_params_check_bigmode_v21,
.get_bay3d_buffd = rkisp_params_get_bay3d_buffd_v21,
};
int rkisp_init_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev)
{
struct device *dev = params_vdev->dev->dev;
struct rkisp_isp_params_val_v21 *priv_val;
int i, ret;
int i, ret, size;
priv_val = kzalloc(sizeof(*priv_val), GFP_KERNEL);
if (!priv_val)
return -ENOMEM;
params_vdev->isp21_params = vmalloc(sizeof(*params_vdev->isp21_params));
size = sizeof(struct isp21_isp_params_cfg);
if (params_vdev->dev->hw_dev->unite)
size *= ISP_UNITE_MAX;
params_vdev->isp21_params = vmalloc(size);
if (!params_vdev->isp21_params) {
kfree(priv_val);
return -ENOMEM;

1
drivers/media/platform/rockchip/isp/isp_params_v2x.c
View File

@@ -4196,6 +4196,7 @@ rkisp_get_param_size_v2x(struct rkisp_isp_params_vdev *params_vdev,
unsigned int sizes[])
{
sizes[0] = sizeof(struct isp2x_isp_params_cfg);
params_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static void

250
drivers/media/platform/rockchip/isp/isp_params_v32.c
View File

@@ -49,10 +49,7 @@ static inline void
isp3_param_write(struct rkisp_isp_params_vdev *params_vdev,
u32 value, u32 addr, u32 id)
{
if (id == ISP3_LEFT)
rkisp_write(params_vdev->dev, addr, value, false);
else
rkisp_next_write(params_vdev->dev, addr, value, false);
rkisp_idx_write(params_vdev->dev, addr, value, id, false);
}
static inline u32
@@ -64,45 +61,27 @@ isp3_param_read_direct(struct rkisp_isp_params_vdev *params_vdev, u32 addr)
static inline u32
isp3_param_read(struct rkisp_isp_params_vdev *params_vdev, u32 addr, u32 id)
{
u32 val;
if (id == ISP3_LEFT)
val = rkisp_read(params_vdev->dev, addr, false);
else
val = rkisp_next_read(params_vdev->dev, addr, false);
return val;
return rkisp_idx_read(params_vdev->dev, addr, id, false);
}
static inline u32
isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev, u32 addr, u32 id)
{
u32 val;
if (id == ISP3_LEFT)
val = rkisp_read_reg_cache(params_vdev->dev, addr);
else
val = rkisp_next_read_reg_cache(params_vdev->dev, addr);
return val;
return rkisp_idx_read_reg_cache(params_vdev->dev, addr, id);
}
static inline void
isp3_param_set_bits(struct rkisp_isp_params_vdev *params_vdev,
u32 reg, u32 bit_mask, u32 id)
{
if (id == ISP3_LEFT)
rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
else
rkisp_next_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
rkisp_idx_set_bits(params_vdev->dev, reg, 0, bit_mask, id, false);
}
static inline void
isp3_param_clear_bits(struct rkisp_isp_params_vdev *params_vdev,
u32 reg, u32 bit_mask, u32 id)
{
if (id == ISP3_LEFT)
rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false);
else
rkisp_next_clear_bits(params_vdev->dev, reg, bit_mask, false);
rkisp_idx_clear_bits(params_vdev->dev, reg, bit_mask, id, false);
}
static void
@@ -1107,8 +1086,10 @@ isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev,
arg->num_afm_win);
struct isp2x_window win_ae;
if (dev->hw_dev->unite)
if (dev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (dev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
for (i = 0; i < num_of_win; i++) {
h_size = arg->win[i].h_size;
@@ -1367,8 +1348,11 @@ isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev,
ISP_PACK_2SHORT(h_offs, v_offs),
ISP3X_RAWAE_LITE_OFFSET, id);
if (ispdev->hw_dev->unite)
if (ispdev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (ispdev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
h_size = arg->win.h_size;
v_size = arg->win.v_size;
if (!h_size || h_size + h_offs + 1 > width)
@@ -1462,8 +1446,10 @@ isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
ISP_PACK_2SHORT(h_offs, v_offs),
addr + ISP3X_RAWAE_BIG_OFFSET, id);
if (ispdev->hw_dev->unite)
if (ispdev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (ispdev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
h_size = arg->win.h_size;
v_size = arg->win.v_size;
if (!h_size || h_size + h_offs + 1 > width)
@@ -1655,15 +1641,17 @@ isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev,
value |= !!arg->ds16x8_mode_en << 7;
isp3_param_write(params_vdev, value, ISP3X_RAWAWB_BLK_CTRL, id);
h_offs = arg->h_offs & ~0x1;
v_offs = arg->v_offs & ~0x1;
isp3_param_write(params_vdev,
ISP_PACK_2SHORT(h_offs, v_offs),
ISP3X_RAWAWB_WIN_OFFS, id);
if (dev->hw_dev->unite)
if (dev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (dev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
h_size = arg->h_size;
v_size = arg->v_size;
if (!h_size || h_size + h_offs > width)
@@ -2344,8 +2332,11 @@ isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev,
ISP_PACK_2SHORT(h_offs, v_offs),
ISP3X_RAWHIST_LITE_OFFS, id);
if (ispdev->hw_dev->unite)
if (ispdev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (ispdev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
h_size = arg->win.h_size;
v_size = arg->win.v_size;
if (!h_size || h_size + h_offs + 1 > width)
@@ -2499,8 +2490,11 @@ isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev,
ISP_PACK_2SHORT(h_offs, v_offs),
addr + ISP3X_RAWHIST_BIG_OFFS, id);
if (dev->hw_dev->unite)
if (dev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (dev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
h_size = arg->win.h_size;
v_size = arg->win.v_size;
if (!h_size || h_size + h_offs + 1 > width)
@@ -4411,7 +4405,7 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
module_en_update = new_params->module_en_update;
module_ens = new_params->module_ens;
for (id = 0; id <= !!dev->hw_dev->unite; id++) {
for (id = 0; id < dev->unite_div; id++) {
priv_val->buf_3dlut_idx[id] = 0;
for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) {
if (priv_val->buf_3dlut[id][i].mem_priv)
@@ -4438,8 +4432,10 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
u32 val, wrap_line, wsize, div;
bool is_alloc;
if (dev->hw_dev->unite)
if (dev->unite_div > ISP_UNITE_DIV1)
w = ALIGN(isp_sdev->in_crop.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16);
if (dev->unite_div == ISP_UNITE_DIV4)
h = ALIGN(isp_sdev->in_crop.height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16);
priv_val->is_lo8x8 = (!new_params->others.bay3d_cfg.lo4x8_en &&
!new_params->others.bay3d_cfg.lo4x4_en);
@@ -4459,8 +4455,8 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
div = is_bwopt_dis ? 1 : 2;
val = ALIGN(wsize * h / div, 16);
priv_val->bay3d_iir_size = val;
if (dev->hw_dev->unite)
val *= 2;
if (dev->unite_div > ISP_UNITE_DIV1)
val *= dev->unite_div;
is_alloc = true;
if (priv_val->buf_3dnr_iir.mem_priv) {
if (val > priv_val->buf_3dnr_iir.size)
@@ -4482,8 +4478,8 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
/* pixel to Byte and align */
val = ALIGN(val * 2, 16);
priv_val->bay3d_ds_size = val;
if (dev->hw_dev->unite)
val *= 2;
if (dev->unite_div > ISP_UNITE_DIV1)
val *= dev->unite_div;
is_alloc = true;
if (priv_val->buf_3dnr_ds.mem_priv) {
if (val > priv_val->buf_3dnr_ds.size)
@@ -4542,8 +4538,7 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
if (dev->isp_ver == ISP_V32_L) {
if (dev->hw_dev->is_frm_buf && !priv_val->buf_frm.mem_priv) {
priv_val->buf_frm.size = ISP32_LITE_FRM_BUF_SIZE;
if (dev->hw_dev->unite)
priv_val->buf_frm.size *= 2;
priv_val->buf_frm.size *= dev->unite_div;
ret = rkisp_alloc_buffer(dev, &priv_val->buf_frm);
if (ret) {
dev_err(dev->dev, "alloc frm buf fail:%d\n", ret);
@@ -4573,7 +4568,7 @@ free_3dnr:
rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir);
rkisp_free_buffer(dev, &priv_val->buf_3dnr_ds);
err_3dnr:
id = dev->hw_dev->unite ? 1 : 0;
id = dev->unite_div - 1;
i = ISP32_3DLUT_BUF_NUM;
err_3dlut:
for (; id >= 0; id--) {
@@ -4598,6 +4593,8 @@ rkisp_params_check_bigmode_v32_lite(struct rkisp_isp_params_vdev *params_vdev)
int i = 0, j = 0;
bool is_bigmode = false;
if (hw->unite == ISP_UNITE_ONE)
hw->is_frm_buf = true;
using_frm_buf:
if (hw->is_frm_buf) {
ispdev->multi_index = 0;
@@ -4941,15 +4938,14 @@ static void
rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev)
{
struct rkisp_device *dev = params_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_isp_params_val_v32 *priv_val =
(struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
struct rkisp_isp_params_val_v32 *priv_val = params_vdev->priv_val;
struct isp32_isp_params_cfg *params = params_vdev->isp32_params;
int i;
rkisp_params_check_bigmode_v32(params_vdev);
spin_lock(&params_vdev->config_lock);
/* override the default things */
if (!params_vdev->isp32_params->module_cfg_update &&
!params_vdev->isp32_params->module_en_update)
if (!params->module_cfg_update && !params->module_en_update)
dev_warn(dev->dev, "can not get first iq setting in stream on\n");
priv_val->bay3d_en = 0;
@@ -4958,39 +4954,28 @@ rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev)
priv_val->lsc_en = 0;
priv_val->mge_en = 0;
priv_val->lut3d_en = 0;
if (hw->unite) {
if (dev->is_bigmode)
rkisp_next_set_bits(dev, ISP3X_ISP_CTRL1, 0,
ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
__isp_isr_meas_config(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1);
__isp_isr_other_config(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1);
__isp_isr_other_en(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1);
__isp_isr_meas_en(params_vdev, params_vdev->isp32_params + 1, RKISP_PARAMS_ALL, 1);
}
if (dev->is_bigmode)
rkisp_set_bits(dev, ISP3X_ISP_CTRL1, 0,
ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
__isp_isr_meas_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0);
__isp_isr_other_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0);
__isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0);
__isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0);
rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0,
ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
for (i = 0; i < dev->unite_div; i++) {
__isp_isr_meas_config(params_vdev, params + i, RKISP_PARAMS_ALL, i);
__isp_isr_other_config(params_vdev, params + i, RKISP_PARAMS_ALL, i);
__isp_isr_other_en(params_vdev, params + i, RKISP_PARAMS_ALL, i);
__isp_isr_meas_en(params_vdev, params + i, RKISP_PARAMS_ALL, i);
}
spin_unlock(&params_vdev->config_lock);
if (dev->hw_dev->is_frm_buf && priv_val->buf_frm.mem_priv) {
u32 size = priv_val->buf_frm.size;
u32 addr = priv_val->buf_frm.dma_addr;
if (hw->unite) {
size /= 2;
isp3_param_write(params_vdev, size, ISP32L_FRM_BUF_WR_SIZE, 1);
isp3_param_write(params_vdev, addr + size, ISP32L_FRM_BUF_WR_BASE, 1);
isp3_param_write(params_vdev, addr + size, ISP32L_FRM_BUF_RD_BASE, 1);
if (dev->unite_div)
size /= dev->unite_div;
for (i = 0; i < dev->unite_div; i++) {
isp3_param_write(params_vdev, size, ISP32L_FRM_BUF_WR_SIZE, i);
isp3_param_write(params_vdev, addr + size * i, ISP32L_FRM_BUF_WR_BASE, i);
isp3_param_write(params_vdev, addr + size * i, ISP32L_FRM_BUF_RD_BASE, i);
}
isp3_param_write(params_vdev, size, ISP32L_FRM_BUF_WR_SIZE, 0);
isp3_param_write(params_vdev, addr, ISP32L_FRM_BUF_WR_BASE, 0);
isp3_param_write(params_vdev, addr, ISP32L_FRM_BUF_RD_BASE, 0);
}
if (dev->hw_dev->is_single && (dev->isp_state & ISP_START))
rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, CIF_ISP_CTRL_ISP_CFG_UPD, true);
@@ -5004,10 +4989,9 @@ static void rkisp_save_first_param_v32(struct rkisp_isp_params_vdev *params_vdev
static void rkisp_clear_first_param_v32(struct rkisp_isp_params_vdev *params_vdev)
{
u32 size = sizeof(struct isp32_isp_params_cfg);
u32 mult = params_vdev->dev->hw_dev->unite ? ISP_UNITE_MAX : 1;
u32 size = sizeof(struct isp32_isp_params_cfg) * mult;
if (params_vdev->dev->hw_dev->unite)
size *= 2;
memset(params_vdev->isp32_params, 0, size);
}
@@ -5117,9 +5101,10 @@ static void
rkisp_get_param_size_v32(struct rkisp_isp_params_vdev *params_vdev,
unsigned int sizes[])
{
u32 mult = params_vdev->dev->hw_dev->unite ? 2 : 1;
u32 mult = params_vdev->dev->unite_div;
sizes[0] = sizeof(struct isp32_isp_params_cfg) * mult;
params_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static void
@@ -5173,7 +5158,7 @@ rkisp_params_free_meshbuf_v32(struct rkisp_isp_params_vdev *params_vdev,
{
int id;
for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++)
for (id = 0; id < params_vdev->dev->unite_div; id++)
rkisp_deinit_mesh_buf(params_vdev, module_id, id);
}
@@ -5209,9 +5194,9 @@ rkisp_params_info2ddr_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, void *a
priv_val->buf_info_owner = cfg->owner;
return 0;
case RKISP_INFO2DRR_OWNER_GAIN:
ctrl = ISP3X_GAIN_2DDR_mode(cfg->u.gain.gain2ddr_mode);
ctrl = ISP3X_GAIN_2DDR_MODE(cfg->u.gain.gain2ddr_mode);
ctrl |= ISP3X_GAIN_2DDR_EN;
mask = ISP3X_GAIN_2DDR_mode(3);
mask = ISP3X_GAIN_2DDR_MODE(3);
reg = ISP3X_GAIN_CTRL;
if (cfg->wsize)
@@ -5296,6 +5281,26 @@ err:
return -ENOMEM;
}
static void
rkisp_params_get_bay3d_buffd_v32(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_bay3dbuf_info *bay3dbuf)
{
struct rkisp_isp_params_val_v32 *priv_val = params_vdev->priv_val;
struct rkisp_dummy_buffer *buf;
buf = &priv_val->buf_3dnr_iir;
if (rkisp_buf_get_fd(params_vdev->dev, buf, true) < 0)
return;
bay3dbuf->iir_fd = buf->dma_fd;
bay3dbuf->iir_size = buf->size;
buf = &priv_val->buf_3dnr_ds;
if (rkisp_buf_get_fd(params_vdev->dev, buf, true) < 0)
return;
bay3dbuf->u.v32.ds_fd = buf->dma_fd;
bay3dbuf->u.v32.ds_size = buf->size;
}
static void
rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev)
{
@@ -5312,7 +5317,7 @@ rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev)
rkisp_free_buffer(ispdev, &priv_val->buf_lsclut[i]);
for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++)
rkisp_free_buffer(ispdev, &ispdev->stats_vdev.stats_buf[i]);
for (id = 0; id <= !!ispdev->hw_dev->unite; id++) {
for (id = 0; id < ispdev->unite_div; id++) {
for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++)
rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
}
@@ -5328,7 +5333,7 @@ rkisp_params_fop_release_v32(struct rkisp_isp_params_vdev *params_vdev)
{
int id;
for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++) {
for (id = 0; id < params_vdev->dev->unite_div; id++) {
rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_LDCH, id);
rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_CAC, id);
}
@@ -5338,14 +5343,14 @@ rkisp_params_fop_release_v32(struct rkisp_isp_params_vdev *params_vdev)
static void
rkisp_params_disable_isp_v32(struct rkisp_isp_params_vdev *params_vdev)
{
int i;
params_vdev->isp32_params->module_ens = 0;
params_vdev->isp32_params->module_en_update = 0x7ffffffffff;
__isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0);
__isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 0);
if (params_vdev->dev->hw_dev->unite) {
__isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 1);
__isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, 1);
for (i = 0; i < params_vdev->dev->unite_div; i++) {
__isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, i);
__isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL, i);
}
}
@@ -5389,9 +5394,10 @@ static void
rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev,
u32 frame_id, enum rkisp_params_type type)
{
struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
struct rkisp_device *dev = params_vdev->dev;
struct isp32_isp_params_cfg *new_params = NULL;
struct rkisp_buffer *cur_buf = params_vdev->cur_buf;
int i;
spin_lock(&params_vdev->config_lock);
if (!params_vdev->streamon)
@@ -5407,30 +5413,24 @@ rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev,
list_del(&cur_buf->queue);
if (list_empty(&params_vdev->params))
break;
else if (new_params->module_en_update ||
(new_params->module_cfg_update & ISP32_MODULE_FORCE)) {
for (i = 0; i < dev->unite_div; i++) {
/* update en immediately */
__isp_isr_meas_config(params_vdev, new_params, RKISP_PARAMS_ALL, 0);
__isp_isr_other_config(params_vdev, new_params, RKISP_PARAMS_ALL, 0);
__isp_isr_other_en(params_vdev, new_params, RKISP_PARAMS_ALL, 0);
__isp_isr_meas_en(params_vdev, new_params, RKISP_PARAMS_ALL, 0);
new_params->module_cfg_update = 0;
if (hw->unite) {
struct isp32_isp_params_cfg *params = new_params + 1;
__isp_isr_meas_config(params_vdev, params, RKISP_PARAMS_ALL, 1);
__isp_isr_other_config(params_vdev, params, RKISP_PARAMS_ALL, 1);
__isp_isr_other_en(params_vdev, params, RKISP_PARAMS_ALL, 1);
__isp_isr_meas_en(params_vdev, params, RKISP_PARAMS_ALL, 1);
params->module_cfg_update = 0;
if (new_params->module_en_update ||
(new_params->module_cfg_update & ISP32_MODULE_FORCE)) {
__isp_isr_meas_config(params_vdev,
new_params, RKISP_PARAMS_ALL, i);
__isp_isr_other_config(params_vdev,
new_params, RKISP_PARAMS_ALL, i);
__isp_isr_other_en(params_vdev,
new_params, RKISP_PARAMS_ALL, i);
__isp_isr_meas_en(params_vdev,
new_params, RKISP_PARAMS_ALL, i);
new_params->module_cfg_update = 0;
}
}
if (new_params->module_cfg_update &
(ISP32_MODULE_LDCH | ISP32_MODULE_CAC)) {
module_data_abandon(params_vdev, new_params, 0);
if (hw->unite)
module_data_abandon(params_vdev, new_params, 1);
if (new_params->module_cfg_update &
(ISP32_MODULE_LDCH | ISP32_MODULE_CAC))
module_data_abandon(params_vdev, new_params, i);
new_params++;
}
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
cur_buf = NULL;
@@ -5447,21 +5447,16 @@ rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev,
goto unlock;
new_params = (struct isp32_isp_params_cfg *)(cur_buf->vaddr[0]);
if (hw->unite) {
__isp_isr_meas_config(params_vdev, new_params + 1, type, 1);
__isp_isr_other_config(params_vdev, new_params + 1, type, 1);
__isp_isr_other_en(params_vdev, new_params + 1, type, 1);
__isp_isr_meas_en(params_vdev, new_params + 1, type, 1);
for (i = 0; i < dev->unite_div; i++) {
__isp_isr_meas_config(params_vdev, new_params, type, i);
__isp_isr_other_config(params_vdev, new_params, type, i);
__isp_isr_other_en(params_vdev, new_params, type, i);
__isp_isr_meas_en(params_vdev, new_params, type, i);
if (type != RKISP_PARAMS_IMD)
new_params->module_cfg_update = 0;
new_params++;
}
__isp_isr_meas_config(params_vdev, new_params, type, 0);
__isp_isr_other_config(params_vdev, new_params, type, 0);
__isp_isr_other_en(params_vdev, new_params, type, 0);
__isp_isr_meas_en(params_vdev, new_params, type, 0);
if (type != RKISP_PARAMS_IMD) {
new_params->module_cfg_update = 0;
if (hw->unite)
(new_params++)->module_cfg_update = 0;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
cur_buf = NULL;
}
@@ -5475,15 +5470,13 @@ static void
rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
{
u32 value = isp3_param_read(params_vdev, ISP3X_ISP_CTRL1, 0);
int i;
value &= (ISP3X_YNR_FST_FRAME | ISP3X_ADRC_FST_FRAME |
ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME |
ISP3X_RAW3D_FST_FRAME | ISP32_SHP_FST_FRAME);
if (value) {
isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value, 0);
if (params_vdev->dev->hw_dev->unite)
isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value, 1);
}
for (i = 0; i < params_vdev->dev->unite_div && value; i++)
isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value, i);
}
static void
@@ -5529,6 +5522,7 @@ static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
.fop_release = rkisp_params_fop_release_v32,
.check_bigmode = rkisp_params_check_bigmode_v32,
.info2ddr_cfg = rkisp_params_info2ddr_cfg_v32,
.get_bay3d_buffd = rkisp_params_get_bay3d_buffd_v32,
};
int rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev)
@@ -5542,7 +5536,7 @@ int rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev)
size = sizeof(struct isp32_isp_params_cfg);
if (params_vdev->dev->hw_dev->unite)
size *= 2;
size *= ISP_UNITE_MAX;
params_vdev->isp32_params = vmalloc(size);
if (!params_vdev->isp32_params) {
kfree(priv_val);

12
drivers/media/platform/rockchip/isp/isp_params_v32.h
View File

@@ -175,14 +175,14 @@ struct rkisp_isp_params_ops_v32 {
struct rkisp_isp_params_val_v32 {
struct tasklet_struct lsc_tasklet;
struct rkisp_dummy_buffer buf_3dlut[ISP3_UNITE_MAX][ISP32_3DLUT_BUF_NUM];
u32 buf_3dlut_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_3dlut[ISP_UNITE_MAX][ISP32_3DLUT_BUF_NUM];
u32 buf_3dlut_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_ldch[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_ldch[ISP_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_cac[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_cac_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_cac[ISP_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_cac_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_lsclut[ISP32_LSC_LUT_BUF_NUM];
u32 buf_lsclut_idx;

232
drivers/media/platform/rockchip/isp/isp_params_v3x.c
View File

@@ -28,79 +28,49 @@ static inline void
isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev,
u32 value, u32 addr, u32 id)
{
if (id == ISP3_LEFT)
rkisp_write(params_vdev->dev, addr, value, true);
else
rkisp_next_write(params_vdev->dev, addr, value, true);
rkisp_idx_write(params_vdev->dev, addr, value, id, true);
}
static inline void
isp3_param_write(struct rkisp_isp_params_vdev *params_vdev,
u32 value, u32 addr, u32 id)
{
if (id == ISP3_LEFT)
rkisp_write(params_vdev->dev, addr, value, false);
else
rkisp_next_write(params_vdev->dev, addr, value, false);
rkisp_idx_write(params_vdev->dev, addr, value, id, false);
}
static inline u32
isp3_param_read_direct(struct rkisp_isp_params_vdev *params_vdev,
u32 addr, u32 id)
{
u32 val;
if (id == ISP3_LEFT)
val = rkisp_read(params_vdev->dev, addr, true);
else
val = rkisp_next_read(params_vdev->dev, addr, true);
return val;
return rkisp_idx_read(params_vdev->dev, addr, id, true);
}
static inline u32
isp3_param_read(struct rkisp_isp_params_vdev *params_vdev,
u32 addr, u32 id)
{
u32 val;
if (id == ISP3_LEFT)
val = rkisp_read(params_vdev->dev, addr, false);
else
val = rkisp_next_read(params_vdev->dev, addr, false);
return val;
return rkisp_idx_read(params_vdev->dev, addr, id, false);
}
static inline u32
isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev,
u32 addr, u32 id)
{
u32 val;
if (id == ISP3_LEFT)
val = rkisp_read_reg_cache(params_vdev->dev, addr);
else
val = rkisp_next_read_reg_cache(params_vdev->dev, addr);
return val;
return rkisp_idx_read_reg_cache(params_vdev->dev, addr, id);
}
static inline void
isp3_param_set_bits(struct rkisp_isp_params_vdev *params_vdev,
u32 reg, u32 bit_mask, u32 id)
{
if (id == ISP3_LEFT)
rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
else
rkisp_next_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
rkisp_idx_set_bits(params_vdev->dev, reg, 0, bit_mask, id, false);
}
static inline void
isp3_param_clear_bits(struct rkisp_isp_params_vdev *params_vdev,
u32 reg, u32 bit_mask, u32 id)
{
if (id == ISP3_LEFT)
rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false);
else
rkisp_next_clear_bits(params_vdev->dev, reg, bit_mask, false);
rkisp_idx_clear_bits(params_vdev->dev, reg, bit_mask, id, false);
}
static void
@@ -3526,26 +3496,26 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
return;
if (en) {
if (!priv_val->buf_3dnr_iir[id].mem_priv) {
if (!priv_val->buf_3dnr_iir.mem_priv) {
dev_err(ispdev->dev, "no bay3d buffer available\n");
return;
}
value = priv_val->buf_3dnr_iir[id].size;
value = priv_val->bay3d_iir_size;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_SIZE, id);
value = priv_val->buf_3dnr_iir[id].dma_addr;
value = priv_val->buf_3dnr_iir.dma_addr + value * id;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE, id);
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE, id);
value = priv_val->buf_3dnr_cur[id].size;
value = priv_val->bay3d_iir_size;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_SIZE, id);
value = priv_val->buf_3dnr_cur[id].dma_addr;
value = priv_val->buf_3dnr_cur.dma_addr + value * id;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_BASE, id);
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_BASE, id);
value = priv_val->buf_3dnr_ds[id].size;
value = priv_val->bay3d_ds_size;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_SIZE, id);
value = priv_val->buf_3dnr_ds[id].dma_addr;
value = priv_val->buf_3dnr_ds.dma_addr + value * id;
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_BASE, id);
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_RD_BASE, id);
@@ -4164,42 +4134,43 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
if (ispdev->hw_dev->unite)
w = ALIGN(isp_sdev->in_crop.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16);
for (id = 0; id <= !!ispdev->hw_dev->unite; id++) {
size = ALIGN((w + w / 8) * h * 2, 16);
size = ALIGN((w + w / 8) * h * 2, 16);
priv_val->buf_3dnr_iir[id].size = size;
ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
if (ret) {
dev_err(ispdev->dev, "alloc bay3d iir buf fail:%d\n", ret);
goto err_3dnr;
}
priv_val->bay3d_iir_size = size;
if (ispdev->hw_dev->unite)
size *= 2;
priv_val->buf_3dnr_iir.size = size;
ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_iir);
if (ret) {
dev_err(ispdev->dev, "alloc bay3d iir buf fail:%d\n", ret);
goto err_3dnr;
}
priv_val->buf_3dnr_cur.size = size;
ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_cur);
if (ret) {
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir);
dev_err(ispdev->dev, "alloc bay3d cur buf fail:%d\n", ret);
goto err_3dnr;
}
priv_val->buf_3dnr_cur[id].size = size;
ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
if (ret) {
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
dev_err(ispdev->dev, "alloc bay3d cur buf fail:%d\n", ret);
goto err_3dnr;
}
size = 2 * ALIGN(w * h / 64, 16);
priv_val->buf_3dnr_ds[id].size = size;
ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
if (ret) {
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
dev_err(ispdev->dev, "alloc bay3d ds buf fail:%d\n", ret);
goto err_3dnr;
}
size = 2 * ALIGN(w * h / 64, 16);
priv_val->bay3d_ds_size = size;
if (ispdev->hw_dev->unite)
size *= 2;
priv_val->buf_3dnr_ds.size = size;
ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_ds);
if (ret) {
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur);
dev_err(ispdev->dev, "alloc bay3d ds buf fail:%d\n", ret);
goto err_3dnr;
}
}
return 0;
err_3dnr:
for (id -= 1; id >= 0; id--) {
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
}
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds);
id = ispdev->hw_dev->unite ? 1 : 0;
i = ISP3X_3DLUT_BUF_NUM;
err_3dlut:
@@ -4393,20 +4364,45 @@ end:
return ispdev->is_bigmode = is_bigmode;
}
static void
rkisp_params_get_bay3d_buffd_v3x(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_bay3dbuf_info *bay3dbuf)
{
struct rkisp_isp_params_val_v3x *priv_val = params_vdev->priv_val;
struct rkisp_dummy_buffer *buf;
buf = &priv_val->buf_3dnr_iir;
if (rkisp_buf_get_fd(params_vdev->dev, buf, true) < 0)
return;
bay3dbuf->iir_fd = buf->dma_fd;
bay3dbuf->iir_size = buf->size;
buf = &priv_val->buf_3dnr_cur;
if (rkisp_buf_get_fd(params_vdev->dev, buf, true) < 0)
return;
bay3dbuf->u.v30.cur_fd = buf->dma_fd;
bay3dbuf->u.v30.cur_size = buf->size;
buf = &priv_val->buf_3dnr_ds;
if (rkisp_buf_get_fd(params_vdev->dev, buf, true) < 0)
return;
bay3dbuf->u.v30.ds_fd = buf->dma_fd;
bay3dbuf->u.v30.ds_size = buf->size;
}
/* Not called when the camera active, thus not isr protection. */
static void
rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev)
{
struct rkisp_device *dev = params_vdev->dev;
struct rkisp_isp_params_val_v3x *priv_val =
(struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
struct rkisp_isp_params_val_v3x *priv_val = params_vdev->priv_val;
struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params;
int i;
dev->is_bigmode = rkisp_params_check_bigmode_v3x(params_vdev);
spin_lock(&params_vdev->config_lock);
/* override the default things */
if (!params_vdev->isp3x_params->module_cfg_update &&
!params_vdev->isp3x_params->module_en_update)
if (!params->module_cfg_update && !params->module_en_update)
dev_warn(dev->dev, "can not get first iq setting in stream on\n");
priv_val->bay3d_en = 0;
@@ -4415,22 +4411,15 @@ rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev)
priv_val->lsc_en = 0;
priv_val->mge_en = 0;
priv_val->lut3d_en = 0;
if (hw->unite) {
if (dev->is_bigmode)
rkisp_next_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
__isp_isr_meas_config(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
__isp_isr_other_config(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
__isp_isr_other_en(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
__isp_isr_meas_en(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
}
if (dev->is_bigmode)
rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
__isp_isr_meas_config(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
__isp_isr_other_config(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
__isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
__isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0,
ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
for (i = 0; i < dev->unite_div; i++) {
__isp_isr_meas_config(params_vdev, params + i, RKISP_PARAMS_ALL, i);
__isp_isr_other_config(params_vdev, params + i, RKISP_PARAMS_ALL, i);
__isp_isr_other_en(params_vdev, params + i, RKISP_PARAMS_ALL, i);
__isp_isr_meas_en(params_vdev, params + i, RKISP_PARAMS_ALL, i);
}
spin_unlock(&params_vdev->config_lock);
}
@@ -4446,7 +4435,7 @@ static void rkisp_save_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev
static void rkisp_clear_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev)
{
u32 mult = params_vdev->dev->hw_dev->unite ? ISP3_UNITE_MAX : 1;
u32 mult = params_vdev->dev->hw_dev->unite ? ISP_UNITE_MAX : 1;
u32 size = sizeof(struct isp3x_isp_params_cfg) * mult;
memset(params_vdev->isp3x_params, 0, size);
@@ -4545,9 +4534,10 @@ static void
rkisp_get_param_size_v3x(struct rkisp_isp_params_vdev *params_vdev,
unsigned int sizes[])
{
u32 mult = params_vdev->dev->hw_dev->unite ? ISP3_UNITE_MAX : 1;
u32 mult = params_vdev->dev->unite_div;
sizes[0] = sizeof(struct isp3x_isp_params_cfg) * mult;
params_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static void
@@ -4615,10 +4605,10 @@ rkisp_params_stream_stop_v3x(struct rkisp_isp_params_vdev *params_vdev)
priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
tasklet_disable(&priv_val->lsc_tasklet);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds);
for (id = 0; id <= !!ispdev->hw_dev->unite; id++) {
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
for (i = 0; i < ISP3X_3DLUT_BUF_NUM; i++)
rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
}
@@ -4778,43 +4768,14 @@ static void
rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
{
struct rkisp_device *dev = params_vdev->dev;
struct rkisp_hw_dev *hw_dev = dev->hw_dev;
u32 value;
u32 value, i;
value = rkisp_read(dev, ISP3X_ISP_CTRL1, false);
if (value & ISP3X_YNR_FST_FRAME)
rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_YNR_FST_FRAME, false);
if (value & ISP3X_ADRC_FST_FRAME)
rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_ADRC_FST_FRAME, false);
if (value & ISP3X_DHAZ_FST_FRAME)
rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_DHAZ_FST_FRAME, false);
if (value & ISP3X_CNR_FST_FRAME)
rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_CNR_FST_FRAME, false);
if (value & ISP3X_RAW3D_FST_FRAME)
rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_RAW3D_FST_FRAME, false);
if (hw_dev->unite) {
value = rkisp_next_read(dev, ISP3X_ISP_CTRL1, false);
if (value & ISP3X_YNR_FST_FRAME)
rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_YNR_FST_FRAME, false);
if (value & ISP3X_ADRC_FST_FRAME)
rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_ADRC_FST_FRAME, false);
if (value & ISP3X_DHAZ_FST_FRAME)
rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_DHAZ_FST_FRAME, false);
if (value & ISP3X_CNR_FST_FRAME)
rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_CNR_FST_FRAME, false);
if (value & ISP3X_RAW3D_FST_FRAME)
rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_RAW3D_FST_FRAME, false);
}
value &= ISP3X_YNR_FST_FRAME | ISP3X_ADRC_FST_FRAME |
ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME |
ISP3X_RAW3D_FST_FRAME;
for (i = 0; i < dev->unite_div && value; i++)
rkisp_idx_clear_bits(dev, ISP3X_ISP_CTRL1, value, i, false);
}
static void
@@ -4859,6 +4820,7 @@ static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
.stream_stop = rkisp_params_stream_stop_v3x,
.fop_release = rkisp_params_fop_release_v3x,
.check_bigmode = rkisp_params_check_bigmode_v3x,
.get_bay3d_buffd = rkisp_params_get_bay3d_buffd_v3x,
};
int rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev)
@@ -4873,7 +4835,7 @@ int rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev)
size = sizeof(struct isp3x_isp_params_cfg);
if (ispdev->hw_dev->unite)
size *= 2;
size *= ISP_UNITE_MAX;
params_vdev->isp3x_params = vmalloc(size);
if (!params_vdev->isp3x_params) {
kfree(priv_val);

24
drivers/media/platform/rockchip/isp/isp_params_v3x.h
View File

@@ -171,21 +171,23 @@ struct rkisp_isp_params_ops_v3x {
struct rkisp_isp_params_val_v3x {
struct tasklet_struct lsc_tasklet;
struct rkisp_dummy_buffer buf_3dlut[ISP3_UNITE_MAX][ISP3X_3DLUT_BUF_NUM];
u32 buf_3dlut_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_3dlut[ISP_UNITE_MAX][ISP3X_3DLUT_BUF_NUM];
u32 buf_3dlut_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_ldch[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_ldch[ISP_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_lsclut[ISP3_UNITE_MAX][ISP3X_LSC_LUT_BUF_NUM];
u32 buf_lsclut_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_lsclut[ISP_UNITE_MAX][ISP3X_LSC_LUT_BUF_NUM];
u32 buf_lsclut_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_cac[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_cac_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_cac[ISP_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_cac_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_3dnr_iir[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_3dnr_cur[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_3dnr_ds[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_3dnr_iir;
struct rkisp_dummy_buffer buf_3dnr_cur;
struct rkisp_dummy_buffer buf_3dnr_ds;
u32 bay3d_ds_size;
u32 bay3d_iir_size;
bool dhaz_en;
bool drc_en;

22
drivers/media/platform/rockchip/isp/isp_rockit.c
View File

@@ -159,17 +159,19 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
isprk_buf->isp_buf.buff_addr[i] = isprk_buf->buff_addr;
}
if (ispdev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP && isprk_buf) {
val = isprk_buf->buff_addr;
reg = stream->config->mi.y_base_ad_init;
rkisp_write(ispdev, reg, val, false);
if (ispdev->cap_dev.wrap_line && stream->id == RKISP_STREAM_MP) {
if (isprk_buf) {
val = isprk_buf->buff_addr;
reg = stream->config->mi.y_base_ad_init;
rkisp_write(ispdev, reg, val, false);
bytesperline = stream->out_fmt.plane_fmt[0].bytesperline;
val += bytesperline * ispdev->cap_dev.wrap_line;
reg = stream->config->mi.cb_base_ad_init;
rkisp_write(ispdev, reg, val, false);
stream->dummy_buf.dma_addr = isprk_buf->buff_addr;
v4l2_info(&ispdev->v4l2_dev, "rockit wrap buf:0x%x\n", isprk_buf->buff_addr);
bytesperline = stream->out_fmt.plane_fmt[0].bytesperline;
val += bytesperline * ispdev->cap_dev.wrap_line;
reg = stream->config->mi.cb_base_ad_init;
rkisp_write(ispdev, reg, val, false);
stream->dummy_buf.dma_addr = isprk_buf->buff_addr;
v4l2_info(&ispdev->v4l2_dev, "rockit wrap buf:0x%x\n", isprk_buf->buff_addr);
}
return -EINVAL;
}

10
drivers/media/platform/rockchip/isp/isp_stats.c
View File

@@ -44,7 +44,7 @@ static int rkisp_stats_g_fmt_meta_cap(struct file *file, void *priv,
memset(meta, 0, sizeof(*meta));
meta->dataformat = stats_vdev->vdev_fmt.fmt.meta.dataformat;
meta->buffersize = stats_vdev->vdev_fmt.fmt.meta.buffersize;
stats_vdev->ops->get_stat_size(stats_vdev, &meta->buffersize);
return 0;
}
@@ -132,8 +132,7 @@ static int rkisp_stats_vb2_queue_setup(struct vb2_queue *vq,
*num_buffers = clamp_t(u32, *num_buffers, RKISP_ISP_STATS_REQ_BUFS_MIN,
RKISP_ISP_STATS_REQ_BUFS_MAX);
sizes[0] = stats_vdev->vdev_fmt.fmt.meta.buffersize;
stats_vdev->ops->get_stat_size(stats_vdev, sizes);
INIT_LIST_HEAD(&stats_vdev->stat);
return 0;
@@ -166,9 +165,9 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
dev_info(dev->dev,
"tb stat seq:%d meas_type:0x%x\n",
buf->frame_id, buf->meas_type);
memcpy(stats_buf->vaddr[0], buf, sizeof(struct rkisp32_isp_stat_buffer));
memcpy(stats_buf->vaddr[0], buf, size);
buf->meas_type = 0;
vb2_set_plane_payload(vb, 0, sizeof(struct rkisp32_isp_stat_buffer));
vb2_set_plane_payload(vb, 0, size);
vbuf->sequence = buf->frame_id;
spin_unlock_irqrestore(&stats_dev->rd_lock, flags);
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
@@ -286,6 +285,7 @@ static void rkisp_init_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
stats_vdev->rd_buf_idx = 0;
stats_vdev->wr_buf_idx = 0;
memset(stats_vdev->stats_buf, 0, sizeof(stats_vdev->stats_buf));
stats_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_STAT_3A;
if (stats_vdev->dev->isp_ver <= ISP_V13)
rkisp_init_stats_vdev_v1x(stats_vdev);

1
drivers/media/platform/rockchip/isp/isp_stats.h
View File

@@ -34,6 +34,7 @@ struct rkisp_isp_stats_ops {
void (*send_meas)(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work);
void (*rdbk_enable)(struct rkisp_isp_stats_vdev *stats_vdev, bool en);
void (*get_stat_size)(struct rkisp_isp_stats_vdev *stats_vdev, unsigned int sizes[]);
};
/*

14
drivers/media/platform/rockchip/isp/isp_stats_v1x.c
View File

@@ -390,19 +390,23 @@ rkisp_stats_rdbk_enable_v1x(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
{
}
static void
rkisp_get_stat_size_v1x(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
sizes[0] = sizeof(struct rkisp1_stat_buffer);
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp1_stats_isr_v1x,
.send_meas = rkisp1_stats_send_meas_v1x,
.rdbk_enable = rkisp_stats_rdbk_enable_v1x,
.get_stat_size = rkisp_get_stat_size_v1x,
};
void rkisp_init_stats_vdev_v1x(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->vdev_fmt.fmt.meta.dataformat =
V4L2_META_FMT_RK_ISP1_STAT_3A;
stats_vdev->vdev_fmt.fmt.meta.buffersize =
sizeof(struct rkisp1_stat_buffer);
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
if (stats_vdev->dev->isp_ver == ISP_V12 ||
stats_vdev->dev->isp_ver == ISP_V13) {

17
drivers/media/platform/rockchip/isp/isp_stats_v21.c
View File

@@ -1120,10 +1120,19 @@ rkisp_stats_rdbk_enable_v21(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
stats_vdev->rdbk_mode = en;
}
static void
rkisp_get_stat_size_v21(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
sizes[0] = sizeof(struct rkisp_isp2x_stat_buffer);
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v21,
.send_meas = rkisp_stats_send_meas_v21,
.rdbk_enable = rkisp_stats_rdbk_enable_v21,
.get_stat_size = rkisp_get_stat_size_v21,
};
void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev)
@@ -1149,20 +1158,16 @@ void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev)
void rkisp_init_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev)
{
int mult = stats_vdev->dev->hw_dev->unite ? ISP_UNITE_MAX : 1;
int i;
stats_vdev->vdev_fmt.fmt.meta.dataformat =
V4L2_META_FMT_RK_ISP1_STAT_3A;
stats_vdev->vdev_fmt.fmt.meta.buffersize =
sizeof(struct rkisp_isp2x_stat_buffer);
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
stats_vdev->priv_ops = &rkisp_stats_reg_ops_v21;
stats_vdev->rd_stats_from_ddr = false;
for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++) {
stats_vdev->stats_buf[i].is_need_vaddr = true;
stats_vdev->stats_buf[i].size = RKISP_RD_STATS_BUF_SIZE;
stats_vdev->stats_buf[i].size = RKISP_RD_STATS_BUF_SIZE * mult;
rkisp_alloc_buffer(stats_vdev->dev, &stats_vdev->stats_buf[i]);
}
}

14
drivers/media/platform/rockchip/isp/isp_stats_v2x.c
View File

@@ -1458,10 +1458,19 @@ rkisp_stats_rdbk_enable_v2x(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
stats_vdev->rdbk_mode = en;
}
static void
rkisp_get_stat_size_v2x(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
sizes[0] = sizeof(struct rkisp_isp2x_stat_buffer);
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v2x,
.send_meas = rkisp_stats_send_meas_v2x,
.rdbk_enable = rkisp_stats_rdbk_enable_v2x,
.get_stat_size = rkisp_get_stat_size_v2x,
};
void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev)
@@ -1491,11 +1500,6 @@ void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev)
void rkisp_init_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->vdev_fmt.fmt.meta.dataformat =
V4L2_META_FMT_RK_ISP1_STAT_3A;
stats_vdev->vdev_fmt.fmt.meta.buffersize =
sizeof(struct rkisp_isp2x_stat_buffer);
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
stats_vdev->priv_ops = &rkisp_stats_reg_ops_v2x;

62
drivers/media/platform/rockchip/isp/isp_stats_v32.c
View File

@@ -430,6 +430,7 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
unsigned long flags;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 val = 0;
int i;
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
@@ -454,11 +455,9 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
val = stats_vdev->stats_buf[0].dma_addr;
}
if (val) {
rkisp_write(dev, ISP3X_MI_3A_WR_BASE, val, false);
if (dev->hw_dev->unite)
rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE, val + size / 2, false);
}
for (i = 0; i < dev->unite_div && val; i++)
rkisp_idx_write(dev, ISP3X_MI_3A_WR_BASE,
val + i * size / dev->unite_div, i, false);
}
static void
@@ -920,21 +919,30 @@ rkisp_stats_send_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
unsigned int cur_frame_id = meas_work->frame_id;
struct rkisp_buffer *cur_buf = NULL;
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
struct rkisp32_lite_stat_buffer *cur_stat_buf = NULL;
u32 size = sizeof(struct rkisp32_lite_stat_buffer);
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
spin_lock(&stats_vdev->rd_lock);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_LEFT) {
spin_lock(&stats_vdev->rd_lock);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
stats_vdev->cur_buf = cur_buf;
}
spin_unlock(&stats_vdev->rd_lock);
}
spin_unlock(&stats_vdev->rd_lock);
if (cur_buf) {
cur_stat_buf = (struct rkisp32_lite_stat_buffer *)(cur_buf->vaddr[0]);
cur_stat_buf = cur_buf->vaddr[0];
if (dev->unite_index > ISP_UNITE_LEFT)
cur_stat_buf += dev->unite_index;
if ((dev->unite_div == ISP_UNITE_DIV2 && dev->unite_index != ISP_UNITE_RIGHT) ||
(dev->unite_div == ISP_UNITE_DIV4 && dev->unite_index != ISP_UNITE_RIGHT_B))
cur_buf = NULL;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
cur_stat_buf->params.info2ddr.buf_fd = -1;
@@ -972,6 +980,7 @@ rkisp_stats_send_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev,
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
stats_vdev->cur_buf = NULL;
}
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n",
@@ -1064,21 +1073,36 @@ rkisp_stats_rdbk_enable_v32(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
stats_vdev->rdbk_mode = en;
}
static void
rkisp_get_stat_size_v32(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
int mult = stats_vdev->dev->unite_div;
if (stats_vdev->dev->isp_ver == ISP_V32)
sizes[0] = ALIGN(sizeof(struct rkisp32_isp_stat_buffer), 16);
else
sizes[0] = sizeof(struct rkisp32_lite_stat_buffer);
sizes[0] *= mult;
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v32,
.send_meas = rkisp_stats_send_meas_v32,
.rdbk_enable = rkisp_stats_rdbk_enable_v32,
.get_stat_size = rkisp_get_stat_size_v32,
};
void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 div = dev->hw_dev->unite ? 2 : 1;
u32 size = 0, div = dev->unite_div;
if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
rkisp_get_stat_size_v32(stats_vdev, &size);
stats_vdev->stats_buf[0].is_need_vaddr = true;
stats_vdev->stats_buf[0].size = size;
if (rkisp_alloc_buffer(dev, &stats_vdev->stats_buf[0]))
@@ -1107,21 +1131,13 @@ void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev)
{
int mult = stats_vdev->dev->hw_dev->unite ? 2 : 1;
u32 size;
stats_vdev->vdev_fmt.fmt.meta.dataformat =
V4L2_META_FMT_RK_ISP1_STAT_3A;
if (stats_vdev->dev->isp_ver == ISP_V32) {
stats_vdev->priv_ops = &stats_ddr_ops_v32;
stats_vdev->rd_stats_from_ddr = true;
size = ALIGN(sizeof(struct rkisp32_isp_stat_buffer), 16);
} else {
stats_vdev->priv_ops = NULL;
stats_vdev->rd_stats_from_ddr = false;
size = sizeof(struct rkisp32_lite_stat_buffer);
}
stats_vdev->vdev_fmt.fmt.meta.buffersize = size * mult;
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
}

52
drivers/media/platform/rockchip/isp/isp_stats_v3x.c
View File

@@ -33,7 +33,7 @@ static void isp3_module_done(struct rkisp_isp_stats_vdev *stats_vdev,
{
void __iomem *base;
if (id == ISP3_LEFT)
if (id == ISP_UNITE_LEFT || id == ISP_UNITE_LEFT_B)
base = stats_vdev->dev->hw_dev->base_addr;
else
base = stats_vdev->dev->hw_dev->base_next_addr;
@@ -44,13 +44,7 @@ static void isp3_module_done(struct rkisp_isp_stats_vdev *stats_vdev,
static u32 isp3_stats_read(struct rkisp_isp_stats_vdev *stats_vdev,
u32 addr, u32 id)
{
u32 val;
if (id == ISP3_LEFT)
val = rkisp_read(stats_vdev->dev, addr, true);
else
val = rkisp_next_read(stats_vdev->dev, addr, true);
return val;
return rkisp_idx_read(stats_vdev->dev, addr, id, true);
}
static int
@@ -1092,7 +1086,7 @@ rkisp_stats_isr_v3x(struct rkisp_isp_stats_vdev *stats_vdev,
u32 iq_isr_mask = ISP3X_SIAWB_DONE | ISP3X_SIAF_FIN |
ISP3X_EXP_END | ISP3X_SIHST_RDY | ISP3X_AFM_SUM_OF | ISP3X_AFM_LUM_OF;
u32 cur_frame_id, isp_mis_tmp = 0, iq_3a_mask = 0;
u32 wr_buf_idx, temp_isp_ris, temp_isp3a_ris;
u32 i, wr_buf_idx, temp_isp_ris, temp_isp3a_ris;
rkisp_dmarx_get_frame(stats_vdev->dev, &cur_frame_id, NULL, NULL, true);
@@ -1136,12 +1130,10 @@ rkisp_stats_isr_v3x(struct rkisp_isp_stats_vdev *stats_vdev,
stats_vdev->wr_buf_idx = wr_buf_idx;
rkisp_finish_buffer(dev, &stats_vdev->stats_buf[wr_buf_idx]);
rkisp_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[wr_buf_idx].dma_addr, false);
if (dev->hw_dev->unite)
rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[wr_buf_idx].dma_addr +
ISP3X_RD_STATS_BUF_SIZE, false);
for (i = 0; i < dev->unite_div; i++)
rkisp_idx_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[wr_buf_idx].dma_addr +
i * ISP3X_RD_STATS_BUF_SIZE, i, false);
}
if (isp_ris & ISP3X_FRAME) {
@@ -1169,16 +1161,27 @@ rkisp_stats_rdbk_enable_v3x(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
stats_vdev->rdbk_mode = en;
}
static void
rkisp_get_stat_size_v3x(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
int mult = stats_vdev->dev->unite_div;
sizes[0] = sizeof(struct rkisp3x_isp_stat_buffer) * mult;
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v3x,
.send_meas = rkisp_stats_send_meas_v3x,
.rdbk_enable = rkisp_stats_rdbk_enable_v3x,
.get_stat_size = rkisp_get_stat_size_v3x,
};
void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
int i, mult = dev->hw_dev->unite ? 2 : 1;
int i, mult = dev->unite_div;
if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
@@ -1202,12 +1205,10 @@ void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
ISP3X_RD_STATS_BUF_SIZE, false);
rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0,
ISP3X_3A_DDR_WRITE_EN, false);
rkisp_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[0].dma_addr, false);
if (dev->hw_dev->unite)
rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[0].dma_addr +
ISP3X_RD_STATS_BUF_SIZE, false);
for (i = 0; i < dev->unite_div; i++)
rkisp_idx_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[0].dma_addr +
i * ISP3X_RD_STATS_BUF_SIZE, i, false);
return;
err:
@@ -1218,13 +1219,6 @@ err:
void rkisp_init_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
{
int mult = stats_vdev->dev->hw_dev->unite ? 2 : 1;
stats_vdev->vdev_fmt.fmt.meta.dataformat =
V4L2_META_FMT_RK_ISP1_STAT_3A;
stats_vdev->vdev_fmt.fmt.meta.buffersize =
mult * sizeof(struct rkisp3x_isp_stat_buffer);
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
stats_vdev->priv_ops = &stats_reg_ops_v3x;
stats_vdev->rd_stats_from_ddr = false;

224
drivers/media/platform/rockchip/isp/procfs.c
View File

@@ -380,242 +380,242 @@ static void isp30_unite_show(struct rkisp_device *dev, struct seq_file *p)
};
u32 v0, v1;
v0 = rkisp_read(dev, ISP3X_CMSK_CTRL0, false);
v1 = rkisp_next_read(dev, ISP3X_CMSK_CTRL0, false);
v0 = rkisp_idx_read(dev, ISP3X_CMSK_CTRL0, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_CMSK_CTRL0, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"CMSK",
(v0 & 1) ? "ON" : "OFF",
v0, (v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_DPCC0_MODE, false);
v1 = rkisp_next_read(dev, ISP3X_DPCC0_MODE, false);
v0 = rkisp_idx_read(dev, ISP3X_DPCC0_MODE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_DPCC0_MODE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"DPCC0",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_DPCC1_MODE, false);
v1 = rkisp_next_read(dev, ISP3X_DPCC1_MODE, false);
v0 = rkisp_idx_read(dev, ISP3X_DPCC1_MODE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_DPCC1_MODE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"DPCC1",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_DPCC2_MODE, false);
v1 = rkisp_next_read(dev, ISP3X_DPCC2_MODE, false);
v0 = rkisp_idx_read(dev, ISP3X_DPCC2_MODE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_DPCC2_MODE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"DPCC2",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_BLS_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_BLS_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_BLS_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_BLS_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"BLS",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
v1 = rkisp_next_read(dev, ISP3X_ISP_CTRL0, false);
v0 = rkisp_idx_read(dev, ISP3X_ISP_CTRL0, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_ISP_CTRL0, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"SDG",
(v0 & BIT(6)) ? "ON" : "OFF", v0,
(v1 & BIT(6)) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_LSC_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_LSC_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_LSC_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_LSC_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"LSC",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
v1 = rkisp_next_read(dev, ISP3X_ISP_CTRL0, false);
v0 = rkisp_idx_read(dev, ISP3X_ISP_CTRL0, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_ISP_CTRL0, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x) gain:0x%08x 0x%08x, Right %s(0x%x) gain:0x%08x 0x%08x\n",
"AWBGAIN",
(v0 & BIT(7)) ? "ON" : "OFF", v0,
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_G, false),
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_RB, false),
rkisp_idx_read(dev, ISP3X_ISP_AWB_GAIN0_G, ISP_UNITE_LEFT, false),
rkisp_idx_read(dev, ISP3X_ISP_AWB_GAIN0_RB, ISP_UNITE_LEFT, false),
(v1 & BIT(7)) ? "ON" : "OFF", v1,
rkisp_next_read(dev, ISP3X_ISP_AWB_GAIN0_G, false),
rkisp_next_read(dev, ISP3X_ISP_AWB_GAIN0_RB, false));
v0 = rkisp_read(dev, ISP3X_DEBAYER_CONTROL, false);
v1 = rkisp_next_read(dev, ISP3X_DEBAYER_CONTROL, false);
rkisp_idx_read(dev, ISP3X_ISP_AWB_GAIN0_G, ISP_UNITE_RIGHT, false),
rkisp_idx_read(dev, ISP3X_ISP_AWB_GAIN0_RB, ISP_UNITE_RIGHT, false));
v0 = rkisp_idx_read(dev, ISP3X_DEBAYER_CONTROL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_DEBAYER_CONTROL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"DEBAYER",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_CCM_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_CCM_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_CCM_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_CCM_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"CCM",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_GAMMA_OUT_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_GAMMA_OUT_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_GAMMA_OUT_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_GAMMA_OUT_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"GAMMA_OUT",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_CPROC_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_CPROC_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_CPROC_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_CPROC_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"CPROC",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_IMG_EFF_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_IMG_EFF_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_IMG_EFF_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_IMG_EFF_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x) effect:%s, Right %s(0x%x) effect:%s\n",
"IE",
(v0 & 1) ? "ON" : "OFF", v0,
effect[(v0 & CIF_IMG_EFF_CTRL_MODE_MASK) >> 1],
(v1 & 1) ? "ON" : "OFF", v1,
effect[(v1 & CIF_IMG_EFF_CTRL_MODE_MASK) >> 1]);
v0 = rkisp_read(dev, ISP3X_DRC_CTRL0, false);
v1 = rkisp_next_read(dev, ISP3X_DRC_CTRL0, false);
v0 = rkisp_idx_read(dev, ISP3X_DRC_CTRL0, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_DRC_CTRL0, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"HDRDRC",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_HDRMGE_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_HDRMGE_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_HDRMGE_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_HDRMGE_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"HDRMGE",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_BAYNR_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_BAYNR_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_BAYNR_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_BAYNR_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"BAYNR",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_BAY3D_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_BAY3D_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_BAY3D_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_BAY3D_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"BAY3D",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_YNR_GLOBAL_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_YNR_GLOBAL_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"YNR",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_CNR_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_CNR_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_CNR_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_CNR_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"CNR",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_SHARP_EN, false);
v1 = rkisp_next_read(dev, ISP3X_SHARP_EN, false);
v0 = rkisp_idx_read(dev, ISP3X_SHARP_EN, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_SHARP_EN, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"SHARP",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_GIC_CONTROL, false);
v1 = rkisp_next_read(dev, ISP3X_GIC_CONTROL, false);
v0 = rkisp_idx_read(dev, ISP3X_GIC_CONTROL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_GIC_CONTROL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"GIC",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_DHAZ_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_DHAZ_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_DHAZ_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_DHAZ_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"DHAZ",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_3DLUT_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_3DLUT_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_3DLUT_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_3DLUT_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"3DLUT",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_LDCH_STS, false);
v1 = rkisp_next_read(dev, ISP3X_LDCH_STS, false);
v0 = rkisp_idx_read(dev, ISP3X_LDCH_STS, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_LDCH_STS, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"LDCH",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
v1 = rkisp_next_read(dev, ISP3X_ISP_CTRL0, false);
v0 = rkisp_idx_read(dev, ISP3X_ISP_CTRL0, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_ISP_CTRL0, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"CSM",
(v0 & full_range_flg) ? "FULL" : "LIMIT", v0,
(v1 & full_range_flg) ? "FULL" : "LIMIT", v1);
v0 = rkisp_read(dev, ISP3X_CAC_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_CAC_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_CAC_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_CAC_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"CAC",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_GAIN_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_GAIN_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_GAIN_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_GAIN_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"GAIN",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWAF_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_RAWAF_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWAF_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWAF_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWAF",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWAWB_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_RAWAWB_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWAWB_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWAWB_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWAWB",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWAE_LITE_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_RAWAE_LITE_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWAE_LITE_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWAE_LITE_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWAE0",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWAE_BIG2_BASE, false);
v1 = rkisp_next_read(dev, ISP3X_RAWAE_BIG2_BASE, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWAE_BIG2_BASE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWAE_BIG2_BASE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWAE1",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWAE_BIG3_BASE, false);
v1 = rkisp_next_read(dev, ISP3X_RAWAE_BIG3_BASE, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWAE_BIG3_BASE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWAE_BIG3_BASE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWAE2",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWAE_BIG1_BASE, false);
v1 = rkisp_next_read(dev, ISP3X_RAWAE_BIG1_BASE, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWAE_BIG1_BASE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWAE_BIG1_BASE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWAE3",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWHIST_LITE_CTRL, false);
v1 = rkisp_next_read(dev, ISP3X_RAWHIST_LITE_CTRL, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWHIST_LITE_CTRL, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWHIST_LITE_CTRL, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWHIST0",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWHIST_BIG2_BASE, false);
v1 = rkisp_next_read(dev, ISP3X_RAWHIST_BIG2_BASE, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWHIST_BIG2_BASE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWHIST_BIG2_BASE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWHIST1",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWHIST_BIG3_BASE, false);
v1 = rkisp_next_read(dev, ISP3X_RAWHIST_BIG3_BASE, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWHIST_BIG3_BASE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWHIST_BIG3_BASE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWHIST2",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_RAWHIST_BIG1_BASE, false);
v1 = rkisp_next_read(dev, ISP3X_RAWHIST_BIG1_BASE, false);
v0 = rkisp_idx_read(dev, ISP3X_RAWHIST_BIG1_BASE, ISP_UNITE_LEFT, false);
v1 = rkisp_idx_read(dev, ISP3X_RAWHIST_BIG1_BASE, ISP_UNITE_RIGHT, false);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"RAWHIST3",
(v0 & 1) ? "ON" : "OFF", v0,
(v1 & 1) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_ISP_CTRL1, true);
v1 = rkisp_next_read(dev, ISP3X_ISP_CTRL1, true);
v0 = rkisp_idx_read(dev, ISP3X_ISP_CTRL1, ISP_UNITE_LEFT, true);
v1 = rkisp_idx_read(dev, ISP3X_ISP_CTRL1, ISP_UNITE_RIGHT, true);
seq_printf(p, "%-10s Left %s(0x%x), Right %s(0x%x)\n",
"BigMode",
v0 & BIT(28) ? "ON" : "OFF", v0,
v1 & BIT(28) ? "ON" : "OFF", v1);
v0 = rkisp_read(dev, ISP3X_ISP_DEBUG1, true);
v1 = rkisp_next_read(dev, ISP3X_ISP_DEBUG1, true);
v0 = rkisp_idx_read(dev, ISP3X_ISP_DEBUG1, ISP_UNITE_LEFT, true);
v1 = rkisp_idx_read(dev, ISP3X_ISP_DEBUG1, ISP_UNITE_RIGHT, true);
seq_printf(p, "%-10s space full status group. Left:0x%x Right:0x%x\n"
"\t ibuf2(L:0x%x R:0x%x) ibuf1(L:0x%x R:0x%x)\n"
"\t ibuf0(L:0x%x R:0x%x) mpfbc_infifo(L:0x%x R:0x%x)\n"
@@ -626,8 +626,8 @@ static void isp30_unite_show(struct rkisp_device *dev, struct seq_file *p)
(v0 >> 20) & 0xf, (v1 >> 20) & 0xf, (v0 >> 16) & 0xf, (v1 >> 16) & 0xf,
(v0 >> 12) & 0xf, (v1 >> 12) & 0xf, (v0 >> 8) & 0xf, (v1 >> 8) & 0xf,
(v0 >> 4) & 0xf, (v1 >> 4) & 0xf, v0 & 0xf, v1 & 0xf);
v0 = rkisp_read(dev, ISP3X_ISP_DEBUG2, true);
v1 = rkisp_next_read(dev, ISP3X_ISP_DEBUG2, true);
v0 = rkisp_idx_read(dev, ISP3X_ISP_DEBUG2, ISP_UNITE_LEFT, true);
v1 = rkisp_idx_read(dev, ISP3X_ISP_DEBUG2, ISP_UNITE_RIGHT, true);
seq_printf(p, "%-10s Left:0x%x Right:0x%x\n"
"\t bay3d_fifo_full iir(L:%d R:%d) cur(L:%d R:%d)\n"
"\t module outform vertical counter(L:%d R:%d), out frame counter:(L:%d R:%d)\n"
@@ -636,8 +636,8 @@ static void isp30_unite_show(struct rkisp_device *dev, struct seq_file *p)
!!(v0 & BIT(31)), !!(v1 & BIT(31)), !!(v0 & BIT(30)), !!(v1 & BIT(30)),
(v0 >> 16) & 0x3fff, (v1 >> 16) & 0x3fff, (v0 >> 14) & 0x3, (v1 >> 14) & 0x3,
v0 & 0x3fff, v1 & 0x3fff);
v0 = rkisp_read(dev, ISP3X_ISP_DEBUG3, true);
v1 = rkisp_next_read(dev, ISP3X_ISP_DEBUG3, true);
v0 = rkisp_idx_read(dev, ISP3X_ISP_DEBUG3, ISP_UNITE_LEFT, true);
v1 = rkisp_idx_read(dev, ISP3X_ISP_DEBUG3, ISP_UNITE_RIGHT, true);
seq_printf(p, "%-10s isp pipeline group Left:0x%x Right:0x%x\n"
"\t mge(L:%d %d R:%d %d) rawnr(L:%d %d R:%d %d)\n"
"\t bay3d(L:%d %d R:%d %d) tmo(L:%d %d R:%d %d)\n"
@@ -976,14 +976,14 @@ static int isp_show(struct seq_file *p, void *v)
rkisp_read(dev, i + 12, true));
} else {
seq_printf(p, "%04x: %08x %08x %08x %08x | %08x %08x %08x %08x\n", i,
rkisp_read(dev, i, true),
rkisp_read(dev, i + 4, true),
rkisp_read(dev, i + 8, true),
rkisp_read(dev, i + 12, true),
rkisp_next_read(dev, i, true),
rkisp_next_read(dev, i + 4, true),
rkisp_next_read(dev, i + 8, true),
rkisp_next_read(dev, i + 12, true));
rkisp_idx_read(dev, i, ISP_UNITE_LEFT, true),
rkisp_idx_read(dev, i + 4, ISP_UNITE_LEFT, true),
rkisp_idx_read(dev, i + 8, ISP_UNITE_LEFT, true),
rkisp_idx_read(dev, i + 12, ISP_UNITE_LEFT, true),
rkisp_idx_read(dev, i, ISP_UNITE_RIGHT, true),
rkisp_idx_read(dev, i + 4, ISP_UNITE_RIGHT, true),
rkisp_idx_read(dev, i + 8, ISP_UNITE_RIGHT, true),
rkisp_idx_read(dev, i + 12, ISP_UNITE_RIGHT, true));
}
}
}
@@ -1009,26 +1009,26 @@ static void rkisp_proc_dump_mem(struct rkisp_device *dev)
if (dev->isp_ver == ISP_V30) {
struct rkisp_isp_params_val_v3x *p = dev->params_vdev.priv_val;
if (p->buf_3dnr_iir[0].mem_priv) {
if (!p->buf_3dnr_iir[0].is_need_vaddr)
p->buf_3dnr_iir[0].vaddr =
g_ops->vaddr(NULL, p->buf_3dnr_iir[0].mem_priv);
iir_addr = p->buf_3dnr_iir[0].vaddr;
iir_size = p->buf_3dnr_iir[0].size;
if (p->buf_3dnr_iir.mem_priv) {
if (!p->buf_3dnr_iir.is_need_vaddr)
p->buf_3dnr_iir.vaddr =
g_ops->vaddr(NULL, p->buf_3dnr_iir.mem_priv);
iir_addr = p->buf_3dnr_iir.vaddr;
iir_size = p->buf_3dnr_iir.size;
}
if (p->buf_3dnr_cur[0].mem_priv) {
if (!p->buf_3dnr_cur[0].is_need_vaddr)
p->buf_3dnr_cur[0].vaddr =
g_ops->vaddr(NULL, p->buf_3dnr_cur[0].mem_priv);
cur_addr = p->buf_3dnr_cur[0].vaddr;
cur_size = p->buf_3dnr_cur[0].size;
if (p->buf_3dnr_cur.mem_priv) {
if (!p->buf_3dnr_cur.is_need_vaddr)
p->buf_3dnr_cur.vaddr =
g_ops->vaddr(NULL, p->buf_3dnr_cur.mem_priv);
cur_addr = p->buf_3dnr_cur.vaddr;
cur_size = p->buf_3dnr_cur.size;
}
if (p->buf_3dnr_ds[0].mem_priv) {
if (!p->buf_3dnr_ds[0].is_need_vaddr)
p->buf_3dnr_ds[0].vaddr =
g_ops->vaddr(NULL, p->buf_3dnr_ds[0].mem_priv);
ds_addr = p->buf_3dnr_ds[0].vaddr;
ds_size = p->buf_3dnr_ds[0].size;
if (p->buf_3dnr_ds.mem_priv) {
if (!p->buf_3dnr_ds.is_need_vaddr)
p->buf_3dnr_ds.vaddr =
g_ops->vaddr(NULL, p->buf_3dnr_ds.mem_priv);
ds_addr = p->buf_3dnr_ds.vaddr;
ds_size = p->buf_3dnr_ds.size;
}
}

99
drivers/media/platform/rockchip/isp/regs.c
View File

@@ -53,11 +53,10 @@ void rkisp_config_dcrop(struct rkisp_stream *stream,
{
struct rkisp_device *dev = stream->ispdev;
u32 val = stream->config->dual_crop.yuvmode_mask;
bool is_unite = !!dev->hw_dev->unite;
struct v4l2_rect tmp = *rect;
u32 reg;
if (is_unite) {
if (dev->unite_div > ISP_UNITE_DIV1) {
tmp.width /= 2;
if (stream->id == RKISP_STREAM_FBC)
tmp.width &= ~0xf;
@@ -67,6 +66,8 @@ void rkisp_config_dcrop(struct rkisp_stream *stream,
reg = stream->config->dual_crop.h_size;
rkisp_write(dev, reg, tmp.width, false);
if (dev->unite_div == ISP_UNITE_DIV4)
tmp.height /= 2;
reg = stream->config->dual_crop.v_offset;
rkisp_unite_write(dev, reg, tmp.top, false);
reg = stream->config->dual_crop.v_size;
@@ -76,21 +77,23 @@ void rkisp_config_dcrop(struct rkisp_stream *stream,
val |= CIF_DUAL_CROP_GEN_CFG_UPD;
else
val |= CIF_DUAL_CROP_CFG_UPD;
if (is_unite) {
if (dev->unite_div > ISP_UNITE_DIV1) {
u32 right_w, left_w = tmp.width;
reg = stream->config->dual_crop.h_offset;
rkisp_next_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, false);
rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_RIGHT, false);
reg = stream->config->dual_crop.h_size;
right_w = rect->width - left_w;
rkisp_next_write(dev, reg, right_w, false);
rkisp_idx_write(dev, reg, right_w, ISP_UNITE_RIGHT, false);
reg = stream->config->dual_crop.ctrl;
rkisp_next_set_bits(dev, reg, 0, val, false);
rkisp_idx_set_bits(dev, reg, 0, val, ISP_UNITE_RIGHT, false);
/* output with scale */
if (stream->out_fmt.width < rect->width) {
left_w += RKMOUDLE_UNITE_EXTEND_PIXEL;
reg = stream->config->dual_crop.h_size;
rkisp_write(dev, reg, left_w, false);
rkisp_idx_write(dev, reg, left_w, ISP_UNITE_LEFT, false);
}
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"left dcrop (%d, %d) %dx%d\n",
@@ -99,6 +102,23 @@ void rkisp_config_dcrop(struct rkisp_stream *stream,
"right dcrop (%d, %d) %dx%d\n",
RKMOUDLE_UNITE_EXTEND_PIXEL, tmp.top, right_w, tmp.height);
}
if (dev->unite_div == ISP_UNITE_DIV4) {
reg = stream->config->dual_crop.h_offset;
rkisp_idx_write(dev, reg, tmp.left, ISP_UNITE_LEFT_B, false);
rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_RIGHT_B, false);
reg = stream->config->dual_crop.h_size;
rkisp_idx_write(dev, reg, tmp.width, ISP_UNITE_LEFT_B, false);
rkisp_idx_write(dev, reg, tmp.width, ISP_UNITE_RIGHT_B, false);
reg = stream->config->dual_crop.v_offset;
rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_LEFT_B, false);
rkisp_idx_write(dev, reg, RKMOUDLE_UNITE_EXTEND_PIXEL, ISP_UNITE_RIGHT_B, false);
reg = stream->config->dual_crop.ctrl;
rkisp_idx_set_bits(dev, reg, 0, val, ISP_UNITE_LEFT_B, false);
rkisp_idx_set_bits(dev, reg, 0, val, ISP_UNITE_RIGHT_B, false);
}
if (val) {
reg = stream->config->dual_crop.ctrl;
rkisp_set_bits(dev, reg, 0, val, false);
@@ -218,7 +238,7 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
rkisp_write(dev, scale_vc_addr, scale_vc, false);
}
if (dev->hw_dev->unite) {
if (dev->unite_div > ISP_UNITE_DIV1) {
u32 hy_size_reg, hc_size_reg, hy_offs_mi_reg, hc_offs_mi_reg, in_crop_offs_reg;
u32 isp_in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
u32 scl_w = out_y->width / 2;
@@ -271,11 +291,13 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
extend = right_crop_y & ~0x1;
reg = stream->config->dual_crop.h_offset;
rkisp_next_write(dev, reg, extend, false);
rkisp_idx_write(dev, reg, extend, ISP_UNITE_RIGHT, false);
reg = stream->config->dual_crop.h_size;
rkisp_next_write(dev, reg, isp_in_w - extend, false);
rkisp_idx_write(dev, reg, isp_in_w - extend, ISP_UNITE_RIGHT, false);
reg = stream->config->dual_crop.ctrl;
rkisp_next_write(dev, reg, rkisp_next_read_reg_cache(dev, reg), false);
rkisp_idx_write(dev, reg,
rkisp_idx_read_reg_cache(dev, reg, ISP_UNITE_RIGHT),
ISP_UNITE_RIGHT, false);
}
right_scl_in_y = right_crop_y - extend;
right_scl_in_c = right_crop_c - extend;
@@ -288,25 +310,26 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
rkisp_write(dev, in_crop_offs_reg, 0, false);
/* right isp */
rkisp_next_write(dev, hy_size_reg, scl_w, false);
rkisp_next_write(dev, hc_size_reg, scl_w, false);
rkisp_next_write(dev, scale_hy_addr, scale_hy, false);
rkisp_next_write(dev, scale_hcb_addr, scale_hc, false);
rkisp_next_write(dev, scale_hcr_addr, scale_hc, false);
rkisp_next_write(dev, scale_vy_addr, scale_vy, false);
rkisp_next_write(dev, scale_vc_addr, scale_vc, false);
rkisp_next_write(dev, stream->config->rsz.phase_hy, phase_left_y, false);
rkisp_next_write(dev, stream->config->rsz.phase_hc, phase_left_c, false);
rkisp_next_write(dev, stream->config->rsz.phase_vy, 0, false);
rkisp_next_write(dev, stream->config->rsz.phase_vc, 0, false);
rkisp_next_write(dev, hy_offs_mi_reg, scl_w & 15, false);
rkisp_next_write(dev, hc_offs_mi_reg, scl_w & 15, false);
rkisp_next_write(dev, in_crop_offs_reg,
right_scl_in_c << 4 | right_scl_in_y, false);
rkisp_idx_write(dev, hy_size_reg, scl_w, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, hc_size_reg, scl_w, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, scale_hy_addr, scale_hy, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, scale_hcb_addr, scale_hc, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, scale_hcr_addr, scale_hc, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, scale_vy_addr, scale_vy, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, scale_vc_addr, scale_vc, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, stream->config->rsz.phase_hy, phase_left_y, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, stream->config->rsz.phase_hc, phase_left_c, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, stream->config->rsz.phase_vy, 0, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, stream->config->rsz.phase_vc, 0, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, hy_offs_mi_reg, scl_w & 15, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, hc_offs_mi_reg, scl_w & 15, ISP_UNITE_RIGHT, false);
rkisp_idx_write(dev, in_crop_offs_reg,
right_scl_in_c << 4 | right_scl_in_y, ISP_UNITE_RIGHT, false);
rsz_ctrl |= ISP3X_SCL_CLIP_EN;
rkisp_next_write(dev, rsz_ctrl_addr,
rsz_ctrl | ISP3X_SCL_HPHASE_EN | ISP3X_SCL_IN_CLIP_EN, false);
rkisp_idx_write(dev, rsz_ctrl_addr,
rsz_ctrl | ISP3X_SCL_HPHASE_EN | ISP3X_SCL_IN_CLIP_EN,
ISP_UNITE_RIGHT, false);
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"scl:%dx%d, scl factor[hy:%d hc:%d vy:%d vc:%d]\n",
scl_w, out_y->height, scale_hy, scale_hc, scale_vy, scale_vc);
@@ -328,12 +351,12 @@ static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in
u32 rsz_ctrl = 0, val, hy, hc;
bool is_avg = false;
rkisp_write(dev, ISP32_SELF_SCALE_HY_OFFS, 0, true);
rkisp_write(dev, ISP32_SELF_SCALE_HC_OFFS, 0, true);
rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HY, 0, true);
rkisp_write(dev, ISP32_SELF_SCALE_PHASE_HC, 0, true);
rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VY, 0, true);
rkisp_write(dev, ISP32_SELF_SCALE_PHASE_VC, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_HY_OFFS, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_HC_OFFS, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_HY, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_HC, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_VY, 0, true);
rkisp_unite_write(dev, ISP32_SELF_SCALE_PHASE_VC, 0, true);
val = in_y->width | in_y->height << 16;
rkisp_write(dev, ISP32_SELF_SCALE_SRC_SIZE, val, false);
@@ -386,10 +409,10 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
}
/* No phase offset */
rkisp_write(dev, stream->config->rsz.phase_hy, 0, true);
rkisp_write(dev, stream->config->rsz.phase_hc, 0, true);
rkisp_write(dev, stream->config->rsz.phase_vy, 0, true);
rkisp_write(dev, stream->config->rsz.phase_vc, 0, true);
rkisp_unite_write(dev, stream->config->rsz.phase_hy, 0, true);
rkisp_unite_write(dev, stream->config->rsz.phase_hc, 0, true);
rkisp_unite_write(dev, stream->config->rsz.phase_vy, 0, true);
rkisp_unite_write(dev, stream->config->rsz.phase_vc, 0, true);
/* Linear interpolation */
for (i = 0; i < 64; i++) {

11
drivers/media/platform/rockchip/isp/regs_v2x.h
View File

@@ -2696,15 +2696,10 @@ static inline void mi_raw_length(struct rkisp_stream *stream)
stream->config->mi.length == MI_RAW1_RD_LENGTH ||
stream->config->mi.length == MI_RAW2_RD_LENGTH)
is_direct = false;
rkisp_write(stream->ispdev, stream->config->mi.length,
stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
rkisp_unite_write(stream->ispdev, stream->config->mi.length,
stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
if (stream->ispdev->isp_ver == ISP_V21 || stream->ispdev->isp_ver == ISP_V30)
rkisp_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);
if (stream->ispdev->hw_dev->unite) {
rkisp_next_write(stream->ispdev, stream->config->mi.length,
stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
rkisp_next_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);
}
rkisp_unite_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);
}
static inline void rx_force_upd(void __iomem *base)

2
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -2230,7 +2230,7 @@
/* GAIN */
#define ISP3X_GAIN_2DDR_EN BIT(24)
#define ISP3X_GAIN_2DDR_mode(a) (((a) & 0x3) << 25)
#define ISP3X_GAIN_2DDR_MODE(a) (((a) & 0x3) << 25)
/* DPCC */
#define ISP3X_DPCC_WORKING BIT(30)

306
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -219,8 +219,10 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
break;
case ISP_V32_L:
max_w = CIF_ISP_INPUT_W_MAX_V32_L;
max_h = CIF_ISP_INPUT_H_MAX_V32_L;
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_L_UNITE : CIF_ISP_INPUT_W_MAX_V32_L;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
@@ -481,7 +483,7 @@ static void rkisp_dvfs(struct rkisp_device *dev)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
u64 data_rate = 0;
int i, fps, num = 0;
int i, fps, size, num = 0;
if (!hw->is_dvfs)
return;
@@ -492,7 +494,8 @@ static void rkisp_dvfs(struct rkisp_device *dev)
fps = hw->isp_size[i].fps;
if (!fps)
fps = 30;
data_rate += (fps * hw->isp_size[i].size);
size = hw->isp_size[i].size * hw->isp[i]->unite_div;
data_rate += (fps * size);
num++;
}
do_div(data_rate, 1000 * 1000);
@@ -843,6 +846,19 @@ run_next:
else
dev->irq_ends_mask &= ~ISP_FRAME_BP;
if (hw->is_frm_buf) {
val = ISP32L_WR_FRM_BUF_EN | ISP32L_RD_FRM_BUF_EN |
ISP32L_AXI_CONF_RD_ST_MODE | ISP32L_AXI_CONF_RD_DIS |
ISP32L_FRM_BUF_FORCE_UPD;
rkisp_write(dev, ISP32L_AXI_CONF_RD_CTRL, val, true);
val = ISP32L_WR_FRM_BUF_EN | ISP32L_RD_FRM_BUF_EN |
ISP32L_AXI_CONF_RD_ST_MODE | ISP32L_AXI_CONF_RD_DIS |
ISP32L_AXI_CONF_RD_ST;
rkisp_write(dev, ISP32L_AXI_CONF_RD_CTRL, val, true);
udelay(25);
}
val = rkisp_read(dev, CSI2RX_CTRL0, true);
val &= ~SW_IBUF_OP_MODE(0xf);
tmp = SW_IBUF_OP_MODE(dev->rd_mode);
@@ -911,8 +927,10 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
is_try = true;
times = 0;
if (hw->unite == ISP_UNITE_ONE) {
if (dev->sw_rd_cnt < 2)
if (hw->is_multi_overflow && dev->sw_rd_cnt < 2)
isp->unite_index = ISP_UNITE_RIGHT;
else if (hw->is_frm_buf)
isp->unite_index++;
if (!hw->is_multi_overflow || (dev->sw_rd_cnt & 0x1))
is_try = false;
}
@@ -972,24 +990,27 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
hw->is_idle = false;
/* this frame will read count by isp */
isp->sw_rd_cnt = 0;
/* frame double for multi camera resolution out of hardware limit
* first for HW save this camera information, and second to output image
*/
isp->is_frame_double = false;
if (hw->is_multi_overflow &&
(hw->unite == ISP_UNITE_ONE ||
(hw->pre_dev_id != -1 && hw->pre_dev_id != id))) {
isp->is_frame_double = true;
isp->sw_rd_cnt = 1;
times = 0;
}
/* resolution out of hardware limit
* frame is vertically divided into left and right
*/
isp->unite_index = ISP_UNITE_LEFT;
if (hw->unite == ISP_UNITE_ONE) {
isp->sw_rd_cnt *= 2;
isp->sw_rd_cnt += 1;
if (hw->is_multi_overflow) {
/* frame double for multi camera resolution out of hardware limit
* first for HW save this camera information, and second to output image
*/
if ((hw->unite == ISP_UNITE_ONE ||
(hw->pre_dev_id != -1 && hw->pre_dev_id != id))) {
isp->is_frame_double = true;
isp->sw_rd_cnt = 1;
times = 0;
}
/* resolution out of hardware limit
* frame is vertically divided into left and right
*/
if (hw->unite == ISP_UNITE_ONE) {
isp->sw_rd_cnt *= 2;
isp->sw_rd_cnt += 1;
}
} else if (hw->is_frm_buf) {
isp->sw_rd_cnt += (isp->unite_div - 1);
}
/* first frame handle twice for thunderboot
* first output stats to AIQ and wait new params to run second
@@ -1154,15 +1175,17 @@ static void rkisp_config_ism(struct rkisp_device *dev)
{
struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
u32 width = out_crop->width, mult = 1;
u32 unite = dev->hw_dev->unite;
u32 height = out_crop->height;
/* isp2.0 no ism */
if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 ||
dev->isp_ver == ISP_V32_L)
return;
if (unite)
if (dev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (dev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false);
rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false);
rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false);
@@ -1172,7 +1195,7 @@ static void rkisp_config_ism(struct rkisp_device *dev)
rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false);
if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced)
mult = 2;
rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, false);
rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, height / mult, false);
if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
return;
@@ -1507,18 +1530,17 @@ static void rkisp_config_cmsk_dual(struct rkisp_device *dev,
val = ISP3X_SW_CMSK_YUV(left.win[i].cover_color_y,
left.win[i].cover_color_u,
left.win[i].cover_color_v);
rkisp_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
rkisp_next_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
rkisp_unite_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
val = ISP_PACK_2SHORT(left.win[i].h_offs, left.win[i].v_offs);
rkisp_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, ISP_UNITE_LEFT, false);
val = ISP_PACK_2SHORT(left.win[i].h_size, left.win[i].v_size);
rkisp_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, ISP_UNITE_LEFT, false);
val = ISP_PACK_2SHORT(right.win[i].h_offs, right.win[i].v_offs);
rkisp_next_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, ISP_UNITE_RIGHT, false);
val = ISP_PACK_2SHORT(right.win[i].h_size, right.win[i].v_size);
rkisp_next_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, ISP_UNITE_RIGHT, false);
}
w += RKMOUDLE_UNITE_EXTEND_PIXEL;
@@ -1551,33 +1573,34 @@ static void rkisp_config_cmsk_dual(struct rkisp_device *dev,
ctrl = 0;
if (right.win[0].win_en) {
ctrl |= ISP3X_SW_CMSK_EN_MP;
rkisp_next_write(dev, ISP3X_CMSK_CTRL1, right.win[0].win_en, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL1, right.win[0].win_en, ISP_UNITE_RIGHT, false);
val = right.win[0].mode;
rkisp_next_write(dev, ISP3X_CMSK_CTRL4, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL4, val, ISP_UNITE_RIGHT, false);
}
if (right.win[1].win_en) {
ctrl |= ISP3X_SW_CMSK_EN_SP;
rkisp_next_write(dev, ISP3X_CMSK_CTRL2, right.win[1].win_en, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL2, right.win[1].win_en, ISP_UNITE_RIGHT, false);
val = right.win[1].mode;
rkisp_next_write(dev, ISP3X_CMSK_CTRL5, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL5, val, ISP_UNITE_RIGHT, false);
}
if (right.win[2].win_en) {
ctrl |= ISP3X_SW_CMSK_EN_BP;
rkisp_next_write(dev, ISP3X_CMSK_CTRL3, right.win[2].win_en, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL3, right.win[2].win_en, ISP_UNITE_RIGHT, false);
val = right.win[2].mode;
rkisp_next_write(dev, ISP3X_CMSK_CTRL6, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL6, val, ISP_UNITE_RIGHT, false);
}
if (ctrl) {
val = ISP_PACK_2SHORT(w, height);
rkisp_next_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
rkisp_idx_write(dev, ISP3X_CMSK_PIC_SIZE, val, ISP_UNITE_RIGHT, false);
ctrl |= ISP3X_SW_CMSK_EN | ISP3X_SW_CMSK_ORDER_MODE;
}
rkisp_next_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL0, ctrl, ISP_UNITE_RIGHT, false);
val = rkisp_next_read(dev, ISP3X_CMSK_CTRL0, true);
val = rkisp_idx_read(dev, ISP3X_CMSK_CTRL0, ISP_UNITE_RIGHT, true);
if (dev->hw_dev->is_single &&
((val & ISP32_SW_CMSK_EN_PATH) != (val & ISP32_SW_CMSK_EN_PATH_SHD)))
rkisp_next_write(dev, ISP3X_CMSK_CTRL0, val | ISP3X_SW_CMSK_FORCE_UPD, false);
rkisp_idx_write(dev, ISP3X_CMSK_CTRL0, val | ISP3X_SW_CMSK_FORCE_UPD,
ISP_UNITE_RIGHT, false);
}
static void rkisp_config_cmsk(struct rkisp_device *dev)
@@ -1612,20 +1635,20 @@ static int rkisp_config_isp(struct rkisp_device *dev)
struct ispsd_out_fmt *out_fmt;
struct v4l2_rect *in_crop;
struct rkisp_sensor_info *sensor;
bool is_unite = !!dev->hw_dev->unite;
u32 isp_ctrl = 0;
u32 irq_mask = 0;
u32 signal = 0;
u32 acq_mult = 0;
u32 acq_prop = 0;
u32 extend_line = 0;
u32 width;
u32 width, height;
sensor = dev->active_sensor;
in_fmt = &dev->isp_sdev.in_fmt;
out_fmt = &dev->isp_sdev.out_fmt;
in_crop = &dev->isp_sdev.in_crop;
width = in_crop->width;
height = in_crop->height;
if (in_fmt->fmt_type == FMT_BAYER) {
acq_mult = 1;
@@ -1714,8 +1737,10 @@ static int rkisp_config_isp(struct rkisp_device *dev)
rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false);
rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true);
if (is_unite)
if (dev->unite_div > ISP_UNITE_DIV1)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (dev->unite_div == ISP_UNITE_DIV4)
height = height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
/* Acquisition Size */
rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, false);
rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, false);
@@ -1727,11 +1752,11 @@ static int rkisp_config_isp(struct rkisp_device *dev)
rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false);
if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, false);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, false);
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, height / 2, false);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, height / 2, false);
} else {
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, false);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, false);
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, height + extend_line, false);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, height + extend_line, false);
}
/* interrupt mask */
@@ -2035,16 +2060,13 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
/* stop ISP */
val = rkisp_read(dev, CIF_ISP_CTRL, true);
val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_ENABLE);
rkisp_write(dev, CIF_ISP_CTRL, val, true);
rkisp_unite_write(dev, CIF_ISP_CTRL, val, true);
val = rkisp_read(dev, CIF_ISP_CTRL, true);
val |= CIF_ISP_CTRL_ISP_CFG_UPD;
rkisp_write(dev, CIF_ISP_CTRL, val, true);
rkisp_unite_write(dev, CIF_ISP_CTRL, val, true);
rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
if (hw->unite == ISP_UNITE_TWO) {
rkisp_next_write(dev, CIF_ISP_CTRL, val, true);
rkisp_next_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
}
readx_poll_timeout_atomic(readl, base + CIF_ISP_RIS,
val, val & CIF_ISP_OFF, 20, 100);
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
@@ -2072,9 +2094,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
writel(0, base + CIF_ISP_CSI0_MASK2);
writel(0, base + CIF_ISP_CSI0_MASK3);
} else if (dev->isp_ver >= ISP_V20) {
writel(0, base + CSI2RX_CSI2_RESETN);
if (hw->unite == ISP_UNITE_TWO)
rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true);
rkisp_unite_write(dev, CSI2RX_CSI2_RESETN, 0, true);
}
hw->is_dvfs = false;
@@ -2582,6 +2602,8 @@ static void rkisp_isp_sd_try_crop(struct v4l2_subdev *sd,
struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
struct rkisp_device *dev = sd_to_isp_dev(sd);
struct v4l2_rect in_crop = isp_sd->in_crop;
struct rkisp_hw_dev *hw = dev->hw_dev;
u32 size;
crop->left = ALIGN(crop->left, 2);
crop->width = ALIGN(crop->width, 2);
@@ -2590,6 +2612,28 @@ static void rkisp_isp_sd_try_crop(struct v4l2_subdev *sd,
/* update sensor info if sensor link be changed */
rkisp_update_sensor_info(dev);
rkisp_align_sensor_resolution(dev, crop, true);
if (hw->unite == ISP_UNITE_TWO && hw->isp_ver == ISP_V30) {
dev->unite_div = ISP_UNITE_DIV2;
} else {
dev->unite_div = ISP_UNITE_DIV1;
switch (dev->isp_ver) {
case ISP_V30:
size = CIF_ISP_INPUT_W_MAX_V30 * CIF_ISP_INPUT_H_MAX_V30;
break;
case ISP_V32:
size = CIF_ISP_INPUT_W_MAX_V32 * CIF_ISP_INPUT_H_MAX_V32;
break;
case ISP_V32_L:
size = CIF_ISP_INPUT_W_MAX_V32_L * CIF_ISP_INPUT_H_MAX_V32_L;
break;
default:
return;
}
if (crop->width * crop->height > size * 2)
dev->unite_div = ISP_UNITE_DIV4;
else if (crop->width * crop->height > size)
dev->unite_div = ISP_UNITE_DIV2;
}
} else if (pad == RKISP_ISP_PAD_SOURCE_PATH) {
crop->left = clamp_t(u32, crop->left, 0, in_crop.width);
crop->top = clamp_t(u32, crop->top, 0, in_crop.height);
@@ -2654,8 +2698,10 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
break;
case ISP_V32_L:
max_w = CIF_ISP_INPUT_W_MAX_V32_L;
max_h = CIF_ISP_INPUT_H_MAX_V32_L;
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_L_UNITE : CIF_ISP_INPUT_W_MAX_V32_L;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
@@ -2918,8 +2964,9 @@ static void rkisp_rx_qbuf_online(struct rkisp_stream *stream,
{
struct rkisp_device *dev = stream->ispdev;
u32 val = pool->buf.buff_addr[RKISP_PLANE_Y];
u32 reg = stream->config->mi.y_base_ad_init;
rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
rkisp_write(dev, reg, val, false);
if (dev->hw_dev->unite == ISP_UNITE_TWO) {
u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
@@ -2928,7 +2975,7 @@ static void rkisp_rx_qbuf_online(struct rkisp_stream *stream,
else
offs = offs * stream->out_isp_fmt.bpp[0] / 8;
val += offs;
rkisp_next_write(dev, stream->config->mi.y_base_ad_init, val, false);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
}
}
@@ -3394,11 +3441,12 @@ static int rkisp_get_info(struct rkisp_device *dev, struct rkisp_isp_info *info)
if (dev->is_bigmode)
mode |= RKISP_ISP_BIGMODE;
info->mode = mode;
if (dev->hw_dev->unite)
info->act_width = in_crop->width;
if (dev->unite_div > ISP_UNITE_DIV1)
info->act_width = in_crop->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
else
info->act_width = in_crop->width;
info->act_height = in_crop->height;
if (dev->unite_div == ISP_UNITE_DIV4)
info->act_height = in_crop->height / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
return 0;
}
@@ -3480,7 +3528,8 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
rkisp_get_info(isp_dev, arg);
break;
case RKISP_CMD_GET_TB_HEAD_V32:
if (isp_dev->tb_head.complete != RKISP_TB_OK) {
if (isp_dev->tb_head.complete != RKISP_TB_OK ||
(!isp_dev->is_rtt_suspend && !isp_dev->is_pre_on)) {
ret = -EINVAL;
break;
}
@@ -3490,6 +3539,11 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
memcpy(&tb_head_v32->cfg, isp_dev->params_vdev.isp32_params,
sizeof(struct isp32_isp_params_cfg));
break;
case RKISP_CMD_SET_TB_HEAD_V32:
tb_head_v32 = arg;
memcpy(&isp_dev->tb_head, tb_head_v32,
sizeof(struct rkisp_thunderboot_resmem_head));
break;
case RKISP_CMD_GET_SHARED_BUF:
if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
ret = -ENOIOCTLCMD;
@@ -3589,6 +3643,9 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
case RKISP_VICAP_CMD_MODE:
ret = rkisp_set_work_mode_by_vicap(isp_dev, arg);
break;
case RKISP_CMD_GET_BAY3D_BUFFD:
rkisp_params_get_bay3d_buffd(&isp_dev->params_vdev, arg);
break;
default:
ret = -ENOIOCTLCMD;
}
@@ -3601,103 +3658,91 @@ static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
unsigned int cmd, unsigned long arg)
{
void __user *up = compat_ptr(arg);
struct isp2x_csi_trigger trigger;
struct rkisp_thunderboot_resmem resmem;
struct rkisp_ldchbuf_info ldchbuf;
struct rkisp_ldchbuf_size ldchsize;
struct rkisp_meshbuf_info meshbuf;
struct rkisp_meshbuf_size meshsize;
struct rkisp_thunderboot_shmem shmem;
struct isp2x_buf_idxfd idxfd;
struct rkisp_info2ddr info2ddr;
void *pbuf = NULL;
long ret = 0;
u64 module_id;
u32 size = 0;
bool cp_t_us = false, cp_f_us = false;
if (!up && cmd != RKISP_CMD_FREE_SHARED_BUF)
if (!up &&
cmd != RKISP_CMD_FREE_SHARED_BUF &&
cmd != RKISP_CMD_MULTI_DEV_FORCE_ENUM)
return -EINVAL;
switch (cmd) {
case RKISP_CMD_TRIGGER_READ_BACK:
if (copy_from_user(&trigger, up, sizeof(trigger)))
return -EFAULT;
ret = rkisp_ioctl(sd, cmd, &trigger);
size = sizeof(struct isp2x_csi_trigger);
cp_f_us = true;
break;
case RKISP_CMD_GET_SHARED_BUF:
if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
ret = -ENOIOCTLCMD;
break;
}
ret = rkisp_ioctl(sd, cmd, &resmem);
if (!ret && copy_to_user(up, &resmem, sizeof(resmem)))
ret = -EFAULT;
if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP))
return -ENOIOCTLCMD;
size = sizeof(struct rkisp_thunderboot_resmem);
cp_t_us = true;
break;
case RKISP_CMD_FREE_SHARED_BUF:
if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
ret = -ENOIOCTLCMD;
break;
}
ret = rkisp_ioctl(sd, cmd, NULL);
if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP))
return -ENOIOCTLCMD;
case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
break;
case RKISP_CMD_GET_LDCHBUF_INFO:
ret = rkisp_ioctl(sd, cmd, &ldchbuf);
if (!ret && copy_to_user(up, &ldchbuf, sizeof(ldchbuf)))
ret = -EFAULT;
size = sizeof(struct rkisp_ldchbuf_info);
cp_t_us = true;
break;
case RKISP_CMD_SET_LDCHBUF_SIZE:
if (copy_from_user(&ldchsize, up, sizeof(ldchsize)))
return -EFAULT;
ret = rkisp_ioctl(sd, cmd, &ldchsize);
size = sizeof(struct rkisp_ldchbuf_size);
cp_f_us = true;
break;
case RKISP_CMD_GET_MESHBUF_INFO:
if (copy_from_user(&meshbuf, up, sizeof(meshbuf)))
return -EFAULT;
ret = rkisp_ioctl(sd, cmd, &meshbuf);
if (!ret && copy_to_user(up, &meshbuf, sizeof(meshbuf)))
ret = -EFAULT;
size = sizeof(struct rkisp_meshbuf_info);
cp_f_us = true;
cp_t_us = true;
break;
case RKISP_CMD_SET_MESHBUF_SIZE:
if (copy_from_user(&meshsize, up, sizeof(meshsize)))
return -EFAULT;
ret = rkisp_ioctl(sd, cmd, &meshsize);
size = sizeof(struct rkisp_meshbuf_size);
cp_f_us = true;
break;
case RKISP_CMD_GET_SHM_BUFFD:
if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
ret = -ENOIOCTLCMD;
break;
}
if (copy_from_user(&shmem, up, sizeof(shmem)))
return -EFAULT;
ret = rkisp_ioctl(sd, cmd, &shmem);
if (!ret && copy_to_user(up, &shmem, sizeof(shmem)))
ret = -EFAULT;
if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP))
return -ENOIOCTLCMD;
size = sizeof(struct rkisp_thunderboot_shmem);
cp_f_us = true;
cp_t_us = true;
break;
case RKISP_CMD_GET_FBCBUF_FD:
ret = rkisp_ioctl(sd, cmd, &idxfd);
if (!ret && copy_to_user(up, &idxfd, sizeof(idxfd)))
ret = -EFAULT;
size = sizeof(struct isp2x_buf_idxfd);
cp_t_us = true;
break;
case RKISP_CMD_INFO2DDR:
if (copy_from_user(&info2ddr, up, sizeof(info2ddr)))
return -EFAULT;
ret = rkisp_ioctl(sd, cmd, &info2ddr);
if (!ret && copy_to_user(up, &info2ddr, sizeof(info2ddr)))
ret = -EFAULT;
size = sizeof(struct rkisp_info2ddr);
cp_f_us = true;
cp_t_us = true;
break;
case RKISP_CMD_MESHBUF_FREE:
if (copy_from_user(&module_id, up, sizeof(module_id)))
return -EFAULT;
ret = rkisp_ioctl(sd, cmd, &module_id);
size = sizeof(u64);
cp_f_us = true;
break;
case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
ret = rkisp_ioctl(sd, cmd, NULL);
break;
case RKISP_VICAP_CMD_SET_STREAM:
ret = rkisp_ioctl(sd, cmd, NULL);
case RKISP_CMD_GET_BAY3D_BUFFD:
size = sizeof(struct rkisp_bay3dbuf_info);
cp_t_us = true;
break;
default:
ret = -ENOIOCTLCMD;
return -ENOIOCTLCMD;
}
if (size) {
pbuf = kmalloc(size, GFP_KERNEL);
if (!pbuf)
return -ENOMEM;
}
if (cp_f_us && copy_from_user(pbuf, up, size)) {
ret = -EFAULT;
goto free_buf;
}
ret = rkisp_ioctl(sd, cmd, pbuf);
if (!ret && cp_t_us && copy_to_user(up, pbuf, size))
ret = -EFAULT;
free_buf:
kfree(pbuf);
return ret;
}
#endif
@@ -3807,6 +3852,7 @@ int rkisp_register_isp_subdev(struct rkisp_device *isp_dev,
goto err_cleanup_media_entity;
}
isp_dev->unite_div = ISP_UNITE_DIV1;
rkisp_isp_sd_init_default_fmt(isp_sdev);
isp_dev->hdr.sensor = NULL;
isp_dev->isp_state = ISP_STOP;

2
drivers/media/platform/rockchip/isp/rkisp.h
View File

@@ -61,6 +61,8 @@
#define CIF_ISP_INPUT_H_MAX_V32_UNITE 2160
#define CIF_ISP_INPUT_W_MAX_V32_L 4224
#define CIF_ISP_INPUT_H_MAX_V32_L 3136
#define CIF_ISP_INPUT_W_MAX_V32_L_UNITE 8192
#define CIF_ISP_INPUT_H_MAX_V32_L_UNITE 6144
#define CIF_ISP_INPUT_W_MIN 272
#define CIF_ISP_INPUT_H_MIN 256
#define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX

21
drivers/media/platform/rockchip/isp/version.h
View File

@@ -483,6 +483,27 @@
* 20.more time to wait isp end
* 21.add mode for rv1106 suspend without rtt
* 22.fix is_on false cause pm isp die
*
* v2.5.0 (AIQ v5.5.0)
* 1.wrap mode first done don't send event
* 2.fix 4k and dual_sensor pm oneframe error
* 3.isp32 using ktime_get_boottime_ns
* 4.fix wait timeout with thunderboot
* 5.add buf cnt info to procfs
* 6.sync irq_ends
* 7.fix resume mi no enable
* 8.fix isp32 lost buf
* 9.frame start to check and config next buf
* 10.fix isp stop to enable isp ctrl
* 11.fix isp32 buf no update to hw
* 12.add rkisp_buf_dbg
* 13.fix isp stop to read stats buf
* 14.support multiple wrap
* 15.dvbm buf support from rockit
* 16.add RKISP_CMD_SET_TB_HEAD_V32 API
* 17.add ioctl to get bay3d buf
* 18.fix isp32 lite frame buffer data read
* 19.support 8k for isp32 lite
*/
#define RKISP_DRIVER_VERSION RKISP_API_VERSION

4
drivers/mfd/display-serdes/serdes-i2c.c
View File

@@ -31,7 +31,7 @@ int serdes_i2c_set_sequence(struct serdes *serdes)
if (ret < 0) {
SERDES_DBG_MFD("%s failed to write reg %04x, ret %d, again now\n",
serdes->dev,
dev_name(serdes->dev),
serdes->serdes_init_seq->reg_sequence[i].reg, ret);
ret = serdes_reg_write(serdes,
serdes->serdes_init_seq->reg_sequence[i].reg,
@@ -111,7 +111,7 @@ static int serdes_i2c_set_sequence_backup(struct serdes *serdes)
serdes->serdes_backup_seq->reg_sequence[i].def);
if (ret < 0) {
SERDES_DBG_MFD("%s failed to write reg %04x, ret %d, again now\n",
serdes->dev,
dev_name(serdes->dev),
serdes->serdes_backup_seq->reg_sequence[i].reg, ret);
ret = serdes_reg_write(serdes,
serdes->serdes_backup_seq->reg_sequence[i].reg,

5
drivers/misc/rk628/rk628.h
View File

@@ -135,7 +135,8 @@
#define DUAL_DATA_SWAP BIT(6)
#define DEC_DUALEDGE_EN BIT(5)
#define SW_PROGRESS_EN BIT(4)
#define SW_YC_SWAP BIT(3)
#define SW_BT1120_YC_SWAP BIT(3)
#define SW_BT1120_UV_SWAP BIT(2)
#define SW_CAP_EN_ASYNC BIT(1)
#define SW_CAP_EN_PSYNC BIT(0)
#define GRF_RGB_DEC_CON1 0x0044
@@ -541,6 +542,8 @@ struct rk628_combtxphy {
struct rk628_rgb {
struct regulator *vccio_rgb;
bool bt1120_dual_edge;
bool bt1120_yc_swap;
bool bt1120_uv_swap;
};
struct rk628 {

11
drivers/misc/rk628/rk628_hdmitx.c
View File

@@ -741,6 +741,17 @@ static int rk628_hdmi_bridge_attach(struct drm_bridge *bridge,
return ret;
}
if (rk628_input_is_bt1120(hdmi->rk628)) {
u32 bus_format = MEDIA_BUS_FMT_YUYV8_1X16;
ret = drm_display_info_set_bus_formats(&connector->display_info,
&bus_format, 1);
if (ret) {
dev_err(hdmi->dev, "Failed to set bus formats\n");
return ret;
}
}
drm_connector_helper_add(connector,
&rk628_hdmi_connector_helper_funcs);
drm_connector_attach_encoder(connector, bridge->encoder);

22
drivers/misc/rk628/rk628_rgb.c
View File

@@ -16,14 +16,26 @@ int rk628_rgb_parse(struct rk628 *rk628, struct device_node *rgb_np)
{
int ret = 0;
/* input/output: rgb/bt1120 */
rk628->rgb.vccio_rgb = devm_regulator_get_optional(rk628->dev, "vccio-rgb");
if (IS_ERR(rk628->rgb.vccio_rgb))
rk628->rgb.vccio_rgb = NULL;
/* input/output: bt1120 */
if ((rk628_input_is_bt1120(rk628) || rk628_output_is_bt1120(rk628)) &&
of_property_read_bool(rk628->dev->of_node, "bt1120-dual-edge"))
rk628->rgb.bt1120_dual_edge = true;
/* input: bt1120 */
if (rk628_input_is_bt1120(rk628)) {
if (of_property_read_bool(rk628->dev->of_node, "bt1120-yc-swap"))
rk628->rgb.bt1120_yc_swap = true;
if (of_property_read_bool(rk628->dev->of_node, "bt1120-uv-swap"))
rk628->rgb.bt1120_uv_swap = true;
}
/* output: rgb/bt1120 */
if (rk628_output_is_bt1120(rk628) || rk628_output_is_rgb(rk628))
ret = rk628_panel_info_get(rk628, rgb_np);
@@ -300,8 +312,14 @@ static void rk628_bt1120_decoder_enable(struct rk628 *rk628)
SW_BT_DATA_OEN | SW_INPUT_MODE(INPUT_MODE_BT1120));
rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0,
SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN,
SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN);
SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC |
SW_PROGRESS_EN |
SW_BT1120_YC_SWAP |
SW_BT1120_UV_SWAP,
SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC |
SW_PROGRESS_EN |
(rk628->rgb.bt1120_yc_swap ? SW_BT1120_YC_SWAP : 0) |
(rk628->rgb.bt1120_uv_swap ? SW_BT1120_UV_SWAP : 0));
}
static void rk628_bt1120_encoder_enable(struct rk628 *rk628)

90
drivers/soc/rockchip/pm_domains.c
View File

@@ -134,6 +134,96 @@ module_param_named(always_on, pm_domain_always_on, bool, 0644);
MODULE_PARM_DESC(always_on,
"Always keep pm domains power on except for system suspend.");
#if 0
#define NAME_LEN 20
static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd);
static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on);
static void rockchip_pmu_lock(struct rockchip_pm_domain *pd);
static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd);
/*
* power on : echo gpu 1 > /sys/module/pm_domains/parameters/status
* power off: echo gpu 0 > /sys/module/pm_domains/parameters/status
*/
static int pd_set_status(const char *val, const struct kernel_param *kp)
{
struct generic_pm_domain *genpd;
struct rockchip_pm_domain *pd;
char name[NAME_LEN] = { 0 };
int status = 0;
int i;
bool is_on;
if (!g_pmu)
return 0;
if (strlen(val) > (NAME_LEN - 2))
return -EINVAL;
if (sscanf(val, "%s %d", name, &status) != 2) {
pr_info("power on : echo gpu 1 > /sys/module/pm_domains/parameters/status\n");
pr_info("power off: echo gpu 0 > /sys/module/pm_domains/parameters/status\n");
return -EINVAL;
}
for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
genpd = g_pmu->genpd_data.domains[i];
if (!genpd)
continue;
if (strncmp(genpd->name, name, strlen(name)))
continue;
pd = container_of(genpd, struct rockchip_pm_domain, genpd);
pr_info("set %s %d\n", genpd->name, status);
if (!rockchip_pd_power(pd, status)) {
rockchip_pmu_lock(pd);
is_on = rockchip_pmu_domain_is_on(pd);
rockchip_pmu_unlock(pd);
pr_info("get %s %d\n", genpd->name, is_on);
}
break;
}
return 0;
}
/*
* cat /sys/module/pm_domains/parameters/status
*/
static int pd_get_status(char *buffer, const struct kernel_param *kp)
{
struct generic_pm_domain *genpd;
struct rockchip_pm_domain *pd;
int i;
int len = 0;
bool is_on;
if (!g_pmu)
return 0;
for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
genpd = g_pmu->genpd_data.domains[i];
if (!genpd)
continue;
pd = container_of(genpd, struct rockchip_pm_domain, genpd);
rockchip_pmu_lock(pd);
is_on = rockchip_pmu_domain_is_on(pd);
rockchip_pmu_unlock(pd);
len += sprintf(buffer + len, "%s %d\n", genpd->name, is_on);
}
return len;
}
static const struct kernel_param_ops pd_status_ops = {
.set = pd_set_status,
.get = pd_get_status,
};
module_param_cb(status, &pd_status_ops, NULL, 0600);
MODULE_PARM_DESC(status, "Change pd status.");
#endif
static void rockchip_pmu_lock(struct rockchip_pm_domain *pd)
{
mutex_lock(&pd->pmu->mutex);

219
drivers/soc/rockchip/rockchip_amp.c
View File

@@ -26,6 +26,7 @@
#define GPIO_GROUP_PRIO_MAX 3
#define MAX_GIC_SPI_NUM (1020)
#define AMP_GIC_INFO_DUMP 0
#define AMP_GIC_DBG(fmt, arg...) do { if (0) { pr_warn(fmt, ##arg); } } while (0)
enum amp_cpu_ctrl_status {
@@ -39,6 +40,12 @@ enum amp_cpu_ctrl_status {
#define AMP_FLAG_CPU_EL2_HYP BIT(2)
#define AMP_FLAG_CPU_ARM32_T BIT(3)
enum {
GPIO_IRQ_GROUP_DISABLE = 0x0,
GPIO_IRQ_GROUP_EN_BANK_TYPE = 0x1,
GPIO_IRQ_GROUP_EN_GROUP_TYPE = 0x2,
};
struct rkamp_device {
struct device *dev;
struct clk_bulk_data *clks;
@@ -54,14 +61,27 @@ static struct {
u64 cpu_id;
} cpu_boot_info[CONFIG_NR_CPUS];
struct amp_gpio_group_s {
u32 bank_id;
struct amp_gpio_group_prio_group_info {
u32 prio;
u64 irq_aff[AMP_AFF_MAX_CPU];
u32 irq_id[AMP_AFF_MAX_CPU];
u32 en[AMP_AFF_MAX_CPU];
};
struct amp_gpio_group_bank_type_info {
u32 hw_irq;
u32 prio;
u64 aff;
};
struct amp_gpio_group_info_t {
u32 group_en;
u32 bank_id;
struct amp_gpio_group_bank_type_info bank_type_info;
struct amp_gpio_group_prio_group_info prio_group[GPIO_GROUP_PRIO_MAX];
};
struct amp_irq_cfg_s {
u64 aff;
u32 prio;
@@ -78,7 +98,7 @@ static struct amp_gic_ctrl_s {
u32 flag;
} aff_to_cpumask[AMP_AFF_MAX_CLUSTER][AMP_AFF_MAX_CPU];
struct amp_irq_cfg_s irqs_cfg[MAX_GIC_SPI_NUM];
struct amp_gpio_group_s gpio_grp[GPIO_BANK_NUM][GPIO_GROUP_PRIO_MAX];
struct amp_gpio_group_info_t gpio_grp[GPIO_BANK_NUM];
u32 gpio_banks;
} amp_ctrl;
@@ -304,60 +324,103 @@ u64 rockchip_amp_get_irq_aff(u32 irq)
return amp_ctrl.irqs_cfg[irq].aff;
}
static int gic_amp_get_gpio_prio_group_info(struct device_node *np,
struct amp_gic_ctrl_s *amp_ctrl,
int prio_id)
static int amp_gic_get_gpio_group_bank_type_config(struct device_node *np,
struct amp_gic_ctrl_s *amp_ctrl,
struct amp_gpio_group_info_t *gpio_grp)
{
u32 gpio_bank, prio, irq_id;
u32 prio, irq;
u64 irq_aff;
int i, count0, count1;
struct amp_gpio_group_s *gpio_grp;
struct amp_gpio_group_bank_type_info *bank_type_info;
struct amp_irq_cfg_s *irqs_cfg;
if (prio_id >= GPIO_GROUP_PRIO_MAX)
bank_type_info = &gpio_grp->bank_type_info;
if (of_property_read_u32_array(np, "hw-irq", &irq, 1))
return -EINVAL;
if (of_property_read_u32_array(np, "gpio-bank", &gpio_bank, 1))
if (of_property_read_u64_array(np, "hw-irq-cpu-aff", &irq_aff, 1))
return -EINVAL;
if (gpio_bank >= amp_ctrl->gpio_banks)
return -EINVAL;
gpio_grp = &amp_ctrl->gpio_grp[gpio_bank][prio_id];
if (of_property_read_u32_array(np, "prio", &prio, 1))
return -EINVAL;
if (gpio_bank >= GPIO_BANK_NUM)
bank_type_info->aff = irq_aff;
bank_type_info->hw_irq = irq;
bank_type_info->prio = prio;
irqs_cfg = &amp_ctrl->irqs_cfg[irq];
irqs_cfg->prio = prio;
irqs_cfg->aff = irq_aff;
if (amp_ctrl->gic_version == GIC_V2) {
irqs_cfg->cpumask = amp_get_cpumask_bit(irq_aff);
if (!irqs_cfg->cpumask) {
pr_err(" %s: get cpumask error\n", __func__);
return -EINVAL;
}
}
irqs_cfg->amp_flag = 1;
AMP_GIC_DBG(" %s bank-%d: hw-irq-%d aff-%llx(%x) prio-%x flag-%d\n",
__func__, gpio_grp->bank_id, irq, irqs_cfg->aff,
irqs_cfg->cpumask, irqs_cfg->prio, irqs_cfg->amp_flag);
return 0;
}
static int gic_amp_get_gpio_prio_group_config(struct device_node *np,
struct amp_gic_ctrl_s *amp_ctrl,
struct amp_gpio_group_info_t *gpio_grp,
int prio_id)
{
u32 prio, irq_id;
u64 irq_aff;
int i, count0, count1, count2;
struct amp_irq_cfg_s *irqs_cfg;
struct amp_gpio_group_prio_group_info *prio_grp;
if (prio_id >= GPIO_GROUP_PRIO_MAX)
return -EINVAL;
AMP_GIC_DBG("%s: gpio-%d, group prio:%d-%x\n",
__func__, gpio_bank, prio_id, prio);
count0 = of_property_count_u32_elems(np, "girq-id");
count1 = of_property_count_u64_elems(np, "girq-aff");
if (count0 != count1)
if (of_property_read_u32_array(np, "group-prio", &prio, 1))
return -EINVAL;
gpio_grp->prio = prio;
prio_grp = &gpio_grp->prio_group[prio_id];
prio_grp->prio = prio;
count0 = of_property_count_u32_elems(np, "group-irq-id");
count1 = of_property_count_u64_elems(np, "group-irq-aff");
count2 = of_property_count_u32_elems(np, "group-irq-en");
AMP_GIC_DBG(" %s: bank-%d, group prio [%d]=0x%x\n",
__func__, gpio_grp->bank_id, prio_id, prio);
if (!(count0 == count1 && count0 == count2 && count0)) {
pr_err("%s: group-irq count is error(%d %d %d)\n",
__func__, count0, count1, count2);
return -EINVAL;
}
if (count0 >= AMP_AFF_MAX_CPU)
pr_err("%s: prio group is overflow\n", __func__);
for (i = 0; i < count0; i++) {
of_property_read_u32_index(np, "girq-id", i, &irq_id);
gpio_grp->irq_id[i] = irq_id;
of_property_read_u64_index(np, "girq-aff", i, &irq_aff);
of_property_read_u32_index(np, "group-irq-id", i, &irq_id);
prio_grp->irq_id[i] = irq_id;
gpio_grp->irq_aff[i] = irq_aff;
of_property_read_u64_index(np, "group-irq-aff", i, &irq_aff);
prio_grp->irq_aff[i] = irq_aff;
of_property_read_u32_index(np, "girq-en", i, &gpio_grp->en[i]);
of_property_read_u32_index(np, "group-irq-en", i, &prio_grp->en[i]);
irqs_cfg = &amp_ctrl->irqs_cfg[irq_id];
AMP_GIC_DBG(" %s: group cpu-%d, irq-%d: prio-%x, aff-%llx en-%d\n",
__func__, i, gpio_grp->irq_id[i], gpio_grp->prio,
gpio_grp->irq_aff[i], gpio_grp->en[i]);
AMP_GIC_DBG(" %s: cpu_idx-%d irq-%d: prio-%x aff-%llx grp_en-%d\n",
__func__, i, prio_grp->irq_id[i], prio_grp->prio,
prio_grp->irq_aff[i], prio_grp->en[i]);
if (gpio_grp->en[i]) {
irqs_cfg->prio = gpio_grp->prio;
if (prio_grp->en[i]) {
irqs_cfg->prio = prio_grp->prio;
irqs_cfg->aff = irq_aff;
if (amp_ctrl->gic_version == GIC_V2) {
irqs_cfg->cpumask = amp_get_cpumask_bit(irq_aff);
@@ -369,17 +432,17 @@ static int gic_amp_get_gpio_prio_group_info(struct device_node *np,
irqs_cfg->amp_flag = 1;
}
AMP_GIC_DBG(" %s: prio-%x aff-%llx cpumaks-%x flag-%d\n",
__func__, irqs_cfg->prio, irqs_cfg->aff,
irqs_cfg->cpumask, irqs_cfg->amp_flag);
AMP_GIC_DBG(" %s irq-%d: prio-%x aff-%llx(%x) flag-%d\n",
__func__, prio_grp->irq_id[i], irqs_cfg->prio,
irqs_cfg->aff, irqs_cfg->cpumask, irqs_cfg->amp_flag);
}
return 0;
}
static int gic_amp_gpio_group_get_info(struct device_node *group_node,
struct amp_gic_ctrl_s *amp_ctrl,
int idx)
static int amp_gic_get_gpio_group_type_config(struct device_node *group_node,
struct amp_gic_ctrl_s *amp_ctrl,
struct amp_gpio_group_info_t *gpio_grp)
{
int i = 0;
struct device_node *node;
@@ -388,8 +451,8 @@ static int gic_amp_gpio_group_get_info(struct device_node *group_node,
for_each_available_child_of_node(group_node, node) {
if (i >= GPIO_GROUP_PRIO_MAX)
break;
if (!gic_amp_get_gpio_prio_group_info(node, amp_ctrl,
i)) {
if (!gic_amp_get_gpio_prio_group_config(node, amp_ctrl,
gpio_grp, i)) {
i++;
}
}
@@ -397,27 +460,64 @@ static int gic_amp_gpio_group_get_info(struct device_node *group_node,
return 0;
}
static void gic_of_get_gpio_group(struct device_node *np,
struct amp_gic_ctrl_s *amp_ctrl)
static void amp_gic_get_gpio_group_config(struct device_node *node,
struct amp_gic_ctrl_s *amp_ctrl)
{
struct device_node *bank_node;
struct amp_gpio_group_info_t *gpio_grp;
u32 gpio_bank, group_en;
if (of_property_read_u32_array(node, "gpio-bank-id", &gpio_bank, 1))
return;
if (gpio_bank >= amp_ctrl->gpio_banks)
return;
if (of_property_read_u32_array(node, "group-irq-en", &group_en, 1))
return;
gpio_grp = &amp_ctrl->gpio_grp[gpio_bank];
gpio_grp->bank_id = gpio_bank;
gpio_grp->group_en = group_en;
AMP_GIC_DBG("%s: bank-%d group-en-%d\n", __func__, gpio_bank, group_en);
if (group_en == GPIO_IRQ_GROUP_EN_BANK_TYPE) {
bank_node = of_get_child_by_name(node, "bank-type-cfg");
if (!bank_node) {
pr_err("%s: group_irq_en from dtsi is error\n", __func__);
return;
}
amp_gic_get_gpio_group_bank_type_config(bank_node, amp_ctrl, gpio_grp);
of_node_put(bank_node);
} else if (group_en == GPIO_IRQ_GROUP_EN_GROUP_TYPE) {
amp_gic_get_gpio_group_type_config(node, amp_ctrl, gpio_grp);
}
}
static void amp_gic_get_gpios_group_config(struct device_node *np,
struct amp_gic_ctrl_s *amp_ctrl)
{
struct device_node *gpio_group_node, *node;
int i = 0;
if (of_property_read_u32_array(np, "gpio-group-banks",
&amp_ctrl->gpio_banks, 1))
return;
if (amp_ctrl->gpio_banks >= GPIO_BANK_NUM) {
pr_err("%s: gpio_banks is overflow\n", __func__);
return;
}
gpio_group_node = of_get_child_by_name(np, "gpio-group");
if (gpio_group_node) {
for_each_available_child_of_node(gpio_group_node, node) {
if (i >= amp_ctrl->gpio_banks)
break;
if (!gic_amp_gpio_group_get_info(node, amp_ctrl, i))
i++;
amp_gic_get_gpio_group_config(node, amp_ctrl);
}
of_node_put(gpio_group_node);
}
of_node_put(gpio_group_node);
}
static int amp_gic_get_cpumask(struct device_node *np, struct amp_gic_ctrl_s *amp_ctrl)
@@ -518,6 +618,22 @@ static void amp_gic_get_irqs_config(struct device_node *np,
}
}
static void amp_gic_irqs_config_dump(struct amp_gic_ctrl_s *amp_ctrl)
{
int irq;
struct amp_irq_cfg_s *irqs_cfg;
#if !AMP_GIC_INFO_DUMP
return;
#endif
irqs_cfg = amp_ctrl->irqs_cfg;
for (irq = 32; irq < MAX_GIC_SPI_NUM; irq++) {
AMP_GIC_DBG(" %s: irq-%d aff-%llx(%x) prio-%x flag-%d\n",
__func__, irq, irqs_cfg[irq].aff, irqs_cfg[irq].cpumask,
irqs_cfg[irq].prio, irqs_cfg[irq].amp_flag);
}
}
void rockchip_amp_get_gic_info(u32 spis_num, enum gic_type gic_version)
{
struct device_node *np;
@@ -534,8 +650,9 @@ void rockchip_amp_get_gic_info(u32 spis_num, enum gic_type gic_version)
goto exit;
}
gic_of_get_gpio_group(np, &amp_ctrl);
amp_gic_get_gpios_group_config(np, &amp_ctrl);
amp_gic_get_irqs_config(np, &amp_ctrl);
amp_gic_irqs_config_dump(&amp_ctrl);
exit:
of_node_put(np);

144
drivers/usb/dwc3/core.c
View File

@@ -853,8 +853,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc)
if (ret)
goto disable_ref_clk;
ret = clk_prepare_enable(dwc->utmi_clk);
if (ret)
goto disable_susp_clk;
ret = clk_prepare_enable(dwc->pipe_clk);
if (ret)
goto disable_utmi_clk;
return 0;
disable_utmi_clk:
clk_disable_unprepare(dwc->utmi_clk);
disable_susp_clk:
clk_disable_unprepare(dwc->susp_clk);
disable_ref_clk:
clk_disable_unprepare(dwc->ref_clk);
disable_bus_clk:
@@ -864,6 +876,8 @@ disable_bus_clk:
static void dwc3_clk_disable(struct dwc3 *dwc)
{
clk_disable_unprepare(dwc->pipe_clk);
clk_disable_unprepare(dwc->utmi_clk);
clk_disable_unprepare(dwc->susp_clk);
clk_disable_unprepare(dwc->ref_clk);
clk_disable_unprepare(dwc->bus_clk);
@@ -1771,6 +1785,78 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
return edev;
}
static int dwc3_get_clocks(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
if (!dev->of_node)
return 0;
/*
* Clocks are optional, but new DT platforms should support all clocks
* as required by the DT-binding.
* Some devices have different clock names in legacy device trees,
* check for them to retain backwards compatibility.
*/
dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
if (IS_ERR(dwc->bus_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
"could not get bus clock\n");
}
if (dwc->bus_clk == NULL) {
dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
if (IS_ERR(dwc->bus_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
"could not get bus clock\n");
}
}
dwc->ref_clk = devm_clk_get_optional(dev, "ref");
if (IS_ERR(dwc->ref_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
"could not get ref clock\n");
}
if (dwc->ref_clk == NULL) {
dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
if (IS_ERR(dwc->ref_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
"could not get ref clock\n");
}
}
dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
if (IS_ERR(dwc->susp_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
"could not get suspend clock\n");
}
if (dwc->susp_clk == NULL) {
dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
if (IS_ERR(dwc->susp_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
"could not get suspend clock\n");
}
}
/* specific to Rockchip RK3588 */
dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
if (IS_ERR(dwc->utmi_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
"could not get utmi clock\n");
}
/* specific to Rockchip RK3588 */
dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
if (IS_ERR(dwc->pipe_clk)) {
return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
"could not get pipe clock\n");
}
return 0;
}
static int dwc3_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1821,61 +1907,9 @@ static int dwc3_probe(struct platform_device *pdev)
goto put_usb_psy;
}
if (dev->of_node) {
/*
* Clocks are optional, but new DT platforms should support all
* clocks as required by the DT-binding.
* Some devices have different clock names in legacy device trees,
* check for them to retain backwards compatibility.
*/
dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
if (IS_ERR(dwc->bus_clk)) {
ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
"could not get bus clock\n");
goto put_usb_psy;
}
if (dwc->bus_clk == NULL) {
dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
if (IS_ERR(dwc->bus_clk)) {
ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
"could not get bus clock\n");
goto put_usb_psy;
}
}
dwc->ref_clk = devm_clk_get_optional(dev, "ref");
if (IS_ERR(dwc->ref_clk)) {
ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
"could not get ref clock\n");
goto put_usb_psy;
}
if (dwc->ref_clk == NULL) {
dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
if (IS_ERR(dwc->ref_clk)) {
ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
"could not get ref clock\n");
goto put_usb_psy;
}
}
dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
if (IS_ERR(dwc->susp_clk)) {
ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
"could not get suspend clock\n");
goto put_usb_psy;
}
if (dwc->susp_clk == NULL) {
dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
if (IS_ERR(dwc->susp_clk)) {
ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
"could not get suspend clock\n");
goto put_usb_psy;
}
}
}
ret = dwc3_get_clocks(dwc);
if (ret)
goto put_usb_psy;
ret = reset_control_deassert(dwc->reset);
if (ret)

4
drivers/usb/dwc3/core.h
View File

@@ -1004,6 +1004,8 @@ struct dwc3_scratchpad_array {
* @bus_clk: clock for accessing the registers
* @ref_clk: reference clock
* @susp_clk: clock used when the SS phy is in low power (S3) state
* @utmi_clk: clock used for USB2 PHY communication
* @pipe_clk: clock used for USB3 PHY communication
* @reset: reset control
* @regs: base address for our registers
* @regs_size: address space size
@@ -1172,6 +1174,8 @@ struct dwc3 {
struct clk *bus_clk;
struct clk *ref_clk;
struct clk *susp_clk;
struct clk *utmi_clk;
struct clk *pipe_clk;
struct reset_control *reset;

3
drivers/video/rockchip/mpp/mpp_iommu.c
View File

@@ -527,7 +527,8 @@ mpp_iommu_probe(struct device *dev)
goto err_put_group;
}
init_rwsem(&info->rw_sem);
init_rwsem(&info->rw_sem_self);
info->rw_sem = &info->rw_sem_self;
spin_lock_init(&info->dev_lock);
info->dev = dev;
info->pdev = pdev;

11
drivers/video/rockchip/mpp/mpp_iommu.h
View File

@@ -81,7 +81,8 @@ struct mpp_rk_iommu {
struct mpp_dev;
struct mpp_iommu_info {
struct rw_semaphore rw_sem;
struct rw_semaphore *rw_sem;
struct rw_semaphore rw_sem_self;
struct device *dev;
struct platform_device *pdev;
@@ -139,7 +140,7 @@ int mpp_iommu_reserve_iova(struct mpp_iommu_info *info, dma_addr_t iova, size_t
static inline int mpp_iommu_down_read(struct mpp_iommu_info *info)
{
if (info)
down_read(&info->rw_sem);
down_read(info->rw_sem);
return 0;
}
@@ -147,7 +148,7 @@ static inline int mpp_iommu_down_read(struct mpp_iommu_info *info)
static inline int mpp_iommu_up_read(struct mpp_iommu_info *info)
{
if (info)
up_read(&info->rw_sem);
up_read(info->rw_sem);
return 0;
}
@@ -155,7 +156,7 @@ static inline int mpp_iommu_up_read(struct mpp_iommu_info *info)
static inline int mpp_iommu_down_write(struct mpp_iommu_info *info)
{
if (info)
down_write(&info->rw_sem);
down_write(info->rw_sem);
return 0;
}
@@ -163,7 +164,7 @@ static inline int mpp_iommu_down_write(struct mpp_iommu_info *info)
static inline int mpp_iommu_up_write(struct mpp_iommu_info *info)
{
if (info)
up_write(&info->rw_sem);
up_write(info->rw_sem);
return 0;
}

1
include/dt-bindings/soc/rockchip-amp.h
View File

@@ -2,6 +2,5 @@
#ifndef _DT_BINDINGS_SOC_ROCKCHIP_AMP_H
#define _DT_BINDINGS_SOC_ROCKCHIP_AMP_H
#define CPU_GET_AFFINITY(cpu, cluster) ((cpu) << 0 | ((cluster) << 8))
#define GIC_AMP_IRQ_CFG_ROUTE(_irq, _prio, _aff) (_irq) (_prio) (_aff)
#endif

23
include/uapi/linux/rk-isp2-config.h
View File

@@ -11,7 +11,7 @@
#include <linux/types.h>
#include <linux/v4l2-controls.h>
#define RKISP_API_VERSION KERNEL_VERSION(2, 4, 0)
#define RKISP_API_VERSION KERNEL_VERSION(2, 5, 0)
/****************ISP SUBDEV IOCTL*****************************/
@@ -52,11 +52,15 @@
_IOW('V', BASE_VIDIOC_PRIVATE + 11, long long)
/* BASE_VIDIOC_PRIVATE + 12 for RKISP_CMD_GET_TB_HEAD_V32 */
/* BASE_VIDIOC_PRIVATE + 14 for RKISP_CMD_SET_TB_HEAD_V32 */
/* for all isp device stop and no power off but resolution change */
#define RKISP_CMD_MULTI_DEV_FORCE_ENUM \
_IO('V', BASE_VIDIOC_PRIVATE + 13)
#define RKISP_CMD_GET_BAY3D_BUFFD \
_IOR('V', BASE_VIDIOC_PRIVATE + 15, struct rkisp_bay3dbuf_info)
/****************ISP VIDEO IOCTL******************************/
#define RKISP_CMD_GET_CSI_MEMORY_MODE \
@@ -317,6 +321,23 @@ struct isp2x_mesh_head {
__u32 data_oft;
} __attribute__ ((packed));
struct rkisp_bay3dbuf_info {
int iir_fd;
int iir_size;
union {
struct {
int cur_fd;
int cur_size;
int ds_fd;
int ds_size;
} v30;
struct {
int ds_fd;
int ds_size;
} v32;
} u;
} __attribute__ ((packed));
#define RKISP_CMSK_WIN_MAX 12
#define RKISP_CMSK_WIN_MAX_V30 8
#define RKISP_CMSK_MOSAIC_MODE 0

3
include/uapi/linux/rk-isp32-config.h
View File

@@ -14,6 +14,9 @@
#define RKISP_CMD_GET_TB_HEAD_V32 \
_IOR('V', BASE_VIDIOC_PRIVATE + 12, struct rkisp32_thunderboot_resmem_head)
#define RKISP_CMD_SET_TB_HEAD_V32 \
_IOW('V', BASE_VIDIOC_PRIVATE + 14, struct rkisp32_thunderboot_resmem_head)
#define ISP32_MODULE_DPCC ISP3X_MODULE_DPCC
#define ISP32_MODULE_BLS ISP3X_MODULE_BLS
#define ISP32_MODULE_SDG ISP3X_MODULE_SDG