Merge commit 'df9eb20bbf8104f56f2168cbebba212512cb39a4'

* commit 'df9eb20bbf8104f56f2168cbebba212512cb39a4': arm64: dts: rockchip: rk3588-amp: add configs for amp irqs arm64: dts: rockchip: rk3568-amp: add configs for amp irqs soc: rockchip: power-domain: Add pd status module param for debug video: rockchip: mpp: rkvenc2: Fix rw_sem error arm64: dts: rockchip: rk3588-vehicle-evb: maxim support 1080p display arm64: dts: rockchip: rk3588-vehicle-evb-v21/v22: Use vehicle dummy driver for gear selection ASoC: rockchip: rk817-codec: fix pop from DAC_DIG_CLK_DIS and DAC_DIG_CLK_EN misc: rk628: bt1120: add yc-swap and uv-swap property arm64: dts: rockchip: rk3588-evb: rk628 change the interrupt to rise edge trigger misc: rk628: bt1120-2-hdmi: set bus_format for bt1120 Change-Id: If1116aacbe9ac9d4ef3d433fb2e07bac8854dc9b
2026-06-06 19:08:57 +09:00 · 2024-02-29 18:55:15 +08:00
parent 7f72922db0 df9eb20bbf
commit ab55f1c685
13 changed files with 313 additions and 84 deletions
--- a/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi
@@ -3,6 +3,22 @@
 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 */

+#include <dt-bindings/soc/rockchip-amp.h>
+
+#define CPU_GET_AFFINITY(cpu, cluster)		((cpu) << 8)
+#define RSVD0_IRQn				283
+#define RSVD_IRQn(_N)				(RSVD0_IRQn + (_N))
+#define AMP_CPUOFF_REQ_IRQ(cpu)			RSVD_IRQn(11 + (cpu)) /* gic irq: 294 */
+#define GIC_TOUCH_REQ_IRQ(cpu)			(AMP_CPUOFF_REQ_IRQ(4) + cpu) /* gic irq: 298 */
+#define GPIO_IRQ_GROUP_DISABLE			0x0
+#define GPIO_IRQ_GROUP_EN_BANK_TYPE		0x1
+#define GPIO_IRQ_GROUP_EN_GROUP_TYPE		0x2
+#define GPIO4_IRQn				69
+#define GPIO3_IRQn				68
+#define GPIO2_IRQn				67
+#define GPIO1_IRQn				66
+#define GPIO0_IRQn				65
+
 / {
 	rockchip_amp: rockchip-amp {
 		compatible = "rockchip,rk3568-amp";
@@ -14,11 +30,108 @@
 		pinctrl-0 = <&uart4m1_xfer>;
 		status = "okay";

+		amp-irqs = /bits/ 64 <
+			GIC_AMP_IRQ_CFG_ROUTE(152, 0xd0, CPU_GET_AFFINITY(3, 0))
+			GIC_AMP_IRQ_CFG_ROUTE(AMP_CPUOFF_REQ_IRQ(3), 0xd0, CPU_GET_AFFINITY(3, 0))
+			GIC_AMP_IRQ_CFG_ROUTE(GIC_TOUCH_REQ_IRQ(3), 0xd0, CPU_GET_AFFINITY(3, 0))>;
+
+		gpio-group-banks = <5>;
+		gpio-group {
+			status = "disabled";
+			amp-gpio0 {
+				gpio-bank-id = <0>;
+				group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
+				bank-type-cfg {
+					hw-irq = <GPIO0_IRQn>;
+					hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
+					prio = <0xd0>;
+					status = "disabled";
+				};
+			};
+			amp-gpio1 {
+				gpio-bank-id = <1>;
+				group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
+				bank-type-cfg {
+					hw-irq = <GPIO1_IRQn>;
+					hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
+					prio = <0xd0>;
+					status = "disabled";
+				};
+			};
+			amp-gpio2 {
+				gpio-bank-id = <2>;
+				group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
+				bank-type-cfg {
+					hw-irq = <GPIO2_IRQn>;
+					hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
+					prio = <0xd0>;
+					status = "disabled";
+				};
+			};
+
+			amp-gpio3 {
+				gpio-bank-id = <3>;
+				group-irq-en = <GPIO_IRQ_GROUP_EN_BANK_TYPE>;
+				bank-type-cfg {
+					hw-irq = <GPIO3_IRQn>;
+					hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
+					prio = <0xd0>;
+					status = "disabled";
+				};
+			};
+
+			amp-gpio4 {
+				gpio-bank-id = <4>;
+				group-irq-en = <GPIO_IRQ_GROUP_EN_GROUP_TYPE>;
+				bank-type-cfg {
+					hw-irq = <GPIO4_IRQn>;
+					hw-irq-cpu-aff = /bits/ 64 <CPU_GET_AFFINITY(3, 0)>;
+					prio = <0xd0>;
+					status = "disabled";
+				};
+
+				prio-group0 {
+					group-prio = <0x80>;
+					group-irq-id = <RSVD_IRQn(39) RSVD_IRQn(40)
+							RSVD_IRQn(41) GPIO4_IRQn>;
+					group-irq-aff = /bits/ 64 <CPU_GET_AFFINITY(0, 0)
+						CPU_GET_AFFINITY(1, 0)
+						CPU_GET_AFFINITY(2, 0)
+						CPU_GET_AFFINITY(3, 0)>;
+					group-irq-en = <0x1 0x1 0x1 0x1>;
+					status = "disabled";
+				};
+				prio-group1 {
+					group-prio = <0x90>;
+					group-irq-id = <RSVD_IRQn(42) RSVD_IRQn(43)
+							RSVD_IRQn(44) RSVD_IRQn(45)>;
+					group-irq-aff = /bits/ 64 <CPU_GET_AFFINITY(0, 0)
+						CPU_GET_AFFINITY(1, 0)
+						CPU_GET_AFFINITY(2, 0)
+						CPU_GET_AFFINITY(3, 0)>;
+					group-irq-en = <0x0 0x1 0x1 0x1>;
+					status = "disabled";
+				};
+
+				prio-group2 {
+					group-prio = <0xA0>;
+					group-irq-id = <RSVD_IRQn(46) RSVD_IRQn(47)
+							RSVD_IRQn(48) RSVD_IRQn(49)>;
+					group-irq-aff = /bits/ 64 <CPU_GET_AFFINITY(0, 0)
+						CPU_GET_AFFINITY(1, 0)
+						CPU_GET_AFFINITY(2, 0)
+						CPU_GET_AFFINITY(3, 0)>;
+					group-irq-en = <0x1 0x1 0x1 0x1>;
+					status = "disabled";
+				};
+			};
+		};
+
 		amp_cpus: amp-cpus {
 			amp-cpu3 {
 				id = <0x0 0x300>;
 				entry = <0x0 0x2800000>;
-				boot-on = <0>;
+				boot-on = <1>;
 				mode = <0>;
 			};
 		};
--- a/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi
@@ -5,6 +5,8 @@

 #include <dt-bindings/soc/rockchip-amp.h>

+#define CPU_GET_AFFINITY(cpu, cluster)		((cpu) << 8)
+
 / {
 	rockchip_amp: rockchip-amp {
 		compatible = "rockchip,amp";
@@ -17,6 +19,18 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&uart5m0_xfer>;

+		amp-irqs = /bits/ 64 <
+			/* GPIO EXT */
+			GIC_AMP_IRQ_CFG_ROUTE(314, 0xd0, CPU_GET_AFFINITY(3, 0))
+			GIC_AMP_IRQ_CFG_ROUTE(315, 0xd0, CPU_GET_AFFINITY(3, 0))
+			GIC_AMP_IRQ_CFG_ROUTE(316, 0xd0, CPU_GET_AFFINITY(3, 0))
+			GIC_AMP_IRQ_CFG_ROUTE(317, 0xd0, CPU_GET_AFFINITY(3, 0))
+			GIC_AMP_IRQ_CFG_ROUTE(318, 0xd0, CPU_GET_AFFINITY(3, 0))
+			/* UART5 */
+			GIC_AMP_IRQ_CFG_ROUTE(368, 0xd0, CPU_GET_AFFINITY(3, 0))
+			/* MAILBOX */
+			GIC_AMP_IRQ_CFG_ROUTE(100, 0xd0, CPU_GET_AFFINITY(3, 0))>;
+
 		status = "okay";
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts
@@ -108,7 +108,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&rk628_pin_1>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <RK_PB1 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <RK_PB1 IRQ_TYPE_EDGE_RISING>;
 		enable-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
 		reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
 		plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
@@ -148,7 +148,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&rk628_pin>;
 		interrupt-parent = <&gpio2>;
-		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <RK_PC4 IRQ_TYPE_EDGE_RISING>;
 		enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
 		reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
 		plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-rk628-hdmi2csi.dts
@@ -78,7 +78,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&rk628_pin>;
 		interrupt-parent = <&gpio1>;
-		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <RK_PB2 IRQ_TYPE_EDGE_RISING>;
 		enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
 		reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
 		plugin-det-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>;
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts
@@ -35,23 +35,12 @@
 		#sound-dai-cells = <1>;
 		status = "okay";
 	};
-	gpio-keys {
-		compatible = "gpio-keys";
-		autorepeat;

-		reverse {
-			label = "GPIO Key Reverse";
-			linux,code = <KEY_CAMERA_DOWN>;
-			gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-			debounce-interval = <100>;
-		};
-
-		park {
-			label = "GPIO Key Park";
-			linux,code = <KEY_CAMERA>;
-			gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
-			debounce-interval = <100>;
-		};
+	vehicle_dummy: vehicle_dummy {
+		status = "okay";
+		compatible = "rockchip,vehicle-dummy-gpio";
+		reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
 	};
 };

--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22.dts
@@ -299,23 +299,12 @@
 		#sound-dai-cells = <1>;
 		status = "okay";
 	};
-	gpio-keys {
-		compatible = "gpio-keys";
-		autorepeat;

-		reverse {
-			label = "GPIO Key Reverse";
-			linux,code = <KEY_CAMERA_DOWN>;
-			gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-			debounce-interval = <100>;
-		};
-
-		park {
-			label = "GPIO Key Park";
-			linux,code = <KEY_CAMERA>;
-			gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
-			debounce-interval = <100>;
-		};
+	vehicle_dummy: vehicle_dummy {
+		status = "okay";
+		compatible = "rockchip,vehicle-dummy-gpio";
+		reverse-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
+		park-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
 	};

 	vcc3v3_pcie_wifi: vcc3v3-pcie-wifi {
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi
@@ -489,57 +489,57 @@
 			0322 0024
 			//Init Default
 			0326 00E4
-			//HSYNC_WIDTH_L
-			0385 0038
-			//VSYNC_WIDTH_L
-			0386 0008
+			//HSYNC_WIDTH_L	 HSYNC=32
+			0385 0020
+			//VSYNC_WIDTH_L	 VSYNC=2
+			0386 0002
 			//HSYNC_WIDTH_H/VSYNC_WIDTH_H
 			0387 0000
-			//VFP_L
+			//VFP_L	VFP=200
 			03A5 00C8
 			//VBP_H
 			03A7 0000
-			//VFP_H/VBP_L
-			03A6 0020
-			//VRES_L
+			//VFP_H/VBP_L VBP=8
+			03A6 0008
+			//VRES_L VRES=0X02D0=720
 			03A8 00D0
 			//VRES_H
 			03A9 0002
-			//HFP_L
+			//HFP_L	 HFP=56
 			03AA 0038
 			//HBP_H
-			03AC 0002
-			//HFP_H/HBP_L
-			03AB 0000
-			//HRES_L
+			03AC 0003
+			//HFP_H/HBP_L(4bit)	HBP=56
+			03AB 0008
+			//HRES_L HRES=0X0780=1920
 			03AD 0080
 			//HRES_H
 			03AE 0007
 			//Disable FIFO/DESKEW_EN
 			03A4 00C0
-			//HSYNC_WIDTH_L
-			0395 0038
-			//VSYNC_WIDTH_L
-			0396 0008
+			//HSYNC_WIDTH_L	HSYNC=40
+			0395 0028
+			//VSYNC_WIDTH_L	VSYNC=20
+			0396 0014
 			//HSYNC_WIDTH_H/VSYNC_WIDTH_H
 			0397 0000
-			//VFP_L
-			03B1 00C8
+			//VFP_L	 VFP=15
+			03B1 000F
 			//VBP_H
 			03B3 0000
-			//VFP_H/VBP_L
-			03B2 0020
-			//VRES_L
-			03B4 00D0
+			//VFP_H/VBP_L	VBP=10
+			03B2 000A
+			//VRES_L VRES=0X0438=1080
+			03B4 0038
 			//VRES_H
-			03B5 0002
-			//HFP_L
-			03B6 0038
+			03B5 0004
+			//HFP_L	 HFP=140
+			03B6 008C
 			//HBP_H
-			03B8 0002
-			//HFP_H/HBP_L
-			03B7 0000
-			//HRES_L
+			03B8 0006
+			//HFP_H/HBP_L	HBP=100
+			03B7 0004
+			//HRES_L HRES=0X0780=1920
 			03B9 0080
 			//HRES_H
 			03BA 0007
@@ -870,15 +870,15 @@
 			panel-size= <346 194>;

 			panel-timing {
-				clock-frequency = <115200000>;
+				clock-frequency = <148500000>;
 				hactive = <1920>;
-				vactive = <720>;
-				hfront-porch = <56>;
-				hsync-len = <32>;
-				hback-porch = <56>;
-				vfront-porch = <200>;
-				vsync-len = <2>;
-				vback-porch = <8>;
+				vactive = <1080>;
+				hfront-porch = <140>;
+				hsync-len = <40>;
+				hback-porch = <100>;
+				vfront-porch = <15>;
+				vsync-len = <20>;
+				vback-porch = <10>;
 				hsync-active = <0>;
 				vsync-active = <0>;
 				de-active = <0>;
@@ -2434,5 +2434,5 @@

 &vp3 {
 	assigned-clocks = <&cru DCLK_VOP3>;
-	assigned-clock-parents = <&cru PLL_V0PLL>;
+	assigned-clock-parents = <&cru PLL_GPLL>;
 };
--- a/drivers/misc/rk628/rk628.h
+++ b/drivers/misc/rk628/rk628.h
@@ -135,7 +135,8 @@
 #define DUAL_DATA_SWAP			BIT(6)
 #define DEC_DUALEDGE_EN			BIT(5)
 #define SW_PROGRESS_EN			BIT(4)
-#define SW_YC_SWAP			BIT(3)
+#define SW_BT1120_YC_SWAP		BIT(3)
+#define SW_BT1120_UV_SWAP		BIT(2)
 #define SW_CAP_EN_ASYNC			BIT(1)
 #define SW_CAP_EN_PSYNC			BIT(0)
 #define GRF_RGB_DEC_CON1		0x0044
@@ -541,6 +542,8 @@ struct rk628_combtxphy {
 struct rk628_rgb {
 	struct regulator *vccio_rgb;
 	bool bt1120_dual_edge;
+	bool bt1120_yc_swap;
+	bool bt1120_uv_swap;
 };

 struct rk628 {
--- a/drivers/misc/rk628/rk628_hdmitx.c
+++ b/drivers/misc/rk628/rk628_hdmitx.c
@@ -741,6 +741,17 @@ static int rk628_hdmi_bridge_attach(struct drm_bridge *bridge,
 		return ret;
 	}

+	if (rk628_input_is_bt1120(hdmi->rk628)) {
+		u32 bus_format = MEDIA_BUS_FMT_YUYV8_1X16;
+
+		ret = drm_display_info_set_bus_formats(&connector->display_info,
+						       &bus_format, 1);
+		if (ret) {
+			dev_err(hdmi->dev, "Failed to set bus formats\n");
+			return ret;
+		}
+	}
+
 	drm_connector_helper_add(connector,
 				 &rk628_hdmi_connector_helper_funcs);
 	drm_connector_attach_encoder(connector, bridge->encoder);
--- a/drivers/misc/rk628/rk628_rgb.c
+++ b/drivers/misc/rk628/rk628_rgb.c
@@ -16,14 +16,26 @@ int rk628_rgb_parse(struct rk628 *rk628, struct device_node *rgb_np)
 {
 	int ret = 0;

+	/* input/output: rgb/bt1120 */
 	rk628->rgb.vccio_rgb = devm_regulator_get_optional(rk628->dev, "vccio-rgb");
 	if (IS_ERR(rk628->rgb.vccio_rgb))
 		rk628->rgb.vccio_rgb = NULL;

+	/* input/output: bt1120 */
 	if ((rk628_input_is_bt1120(rk628) || rk628_output_is_bt1120(rk628)) &&
 	    of_property_read_bool(rk628->dev->of_node, "bt1120-dual-edge"))
 		rk628->rgb.bt1120_dual_edge = true;

+	/* input: bt1120 */
+	if (rk628_input_is_bt1120(rk628)) {
+		if (of_property_read_bool(rk628->dev->of_node, "bt1120-yc-swap"))
+			rk628->rgb.bt1120_yc_swap = true;
+
+		if (of_property_read_bool(rk628->dev->of_node, "bt1120-uv-swap"))
+			rk628->rgb.bt1120_uv_swap = true;
+	}
+
+	/* output: rgb/bt1120 */
 	if (rk628_output_is_bt1120(rk628) || rk628_output_is_rgb(rk628))
 		ret = rk628_panel_info_get(rk628, rgb_np);

@@ -300,8 +312,14 @@ static void rk628_bt1120_decoder_enable(struct rk628 *rk628)
 			      SW_BT_DATA_OEN | SW_INPUT_MODE(INPUT_MODE_BT1120));
 	rk628_i2c_write(rk628, GRF_CSC_CTRL_CON, SW_Y2R_EN(1));
 	rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0,
-			      SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN,
-			      SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC | SW_PROGRESS_EN);
+			      SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC |
+			      SW_PROGRESS_EN |
+			      SW_BT1120_YC_SWAP |
+			      SW_BT1120_UV_SWAP,
+			      SW_CAP_EN_PSYNC | SW_CAP_EN_ASYNC |
+			      SW_PROGRESS_EN |
+			      (rk628->rgb.bt1120_yc_swap ? SW_BT1120_YC_SWAP : 0) |
+			      (rk628->rgb.bt1120_uv_swap ? SW_BT1120_UV_SWAP : 0));
 }

 static void rk628_bt1120_encoder_enable(struct rk628 *rk628)
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -134,6 +134,96 @@ module_param_named(always_on, pm_domain_always_on, bool, 0644);
 MODULE_PARM_DESC(always_on,
 		 "Always keep pm domains power on except for system suspend.");

+#if 0
+#define NAME_LEN 20
+
+static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd);
+static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on);
+static void rockchip_pmu_lock(struct rockchip_pm_domain *pd);
+static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd);
+
+/*
+ * power on : echo gpu 1 > /sys/module/pm_domains/parameters/status
+ * power off: echo gpu 0 > /sys/module/pm_domains/parameters/status
+ */
+static int pd_set_status(const char *val, const struct kernel_param *kp)
+{
+	struct generic_pm_domain *genpd;
+	struct rockchip_pm_domain *pd;
+	char name[NAME_LEN] = { 0 };
+	int status = 0;
+	int i;
+	bool is_on;
+
+	if (!g_pmu)
+		return 0;
+
+	if (strlen(val) > (NAME_LEN - 2))
+		return -EINVAL;
+
+	if (sscanf(val, "%s %d", name, &status) != 2) {
+		pr_info("power on : echo gpu 1 > /sys/module/pm_domains/parameters/status\n");
+		pr_info("power off: echo gpu 0 > /sys/module/pm_domains/parameters/status\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
+		genpd = g_pmu->genpd_data.domains[i];
+		if (!genpd)
+			continue;
+		if (strncmp(genpd->name, name, strlen(name)))
+			continue;
+		pd = container_of(genpd, struct rockchip_pm_domain, genpd);
+		pr_info("set %s %d\n", genpd->name, status);
+		if (!rockchip_pd_power(pd, status)) {
+			rockchip_pmu_lock(pd);
+			is_on = rockchip_pmu_domain_is_on(pd);
+			rockchip_pmu_unlock(pd);
+			pr_info("get %s %d\n", genpd->name, is_on);
+		}
+		break;
+	}
+
+	return 0;
+}
+
+/*
+ * cat /sys/module/pm_domains/parameters/status
+ */
+static int pd_get_status(char *buffer, const struct kernel_param *kp)
+{
+	struct generic_pm_domain *genpd;
+	struct rockchip_pm_domain *pd;
+	int i;
+	int len = 0;
+	bool is_on;
+
+	if (!g_pmu)
+		return 0;
+
+	for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
+		genpd = g_pmu->genpd_data.domains[i];
+		if (!genpd)
+			continue;
+		pd = container_of(genpd, struct rockchip_pm_domain, genpd);
+		rockchip_pmu_lock(pd);
+		is_on = rockchip_pmu_domain_is_on(pd);
+		rockchip_pmu_unlock(pd);
+		len += sprintf(buffer + len, "%s %d\n", genpd->name, is_on);
+	}
+
+	return len;
+}
+
+static const struct kernel_param_ops pd_status_ops = {
+	.set = pd_set_status,
+	.get = pd_get_status,
+};
+
+module_param_cb(status, &pd_status_ops, NULL, 0600);
+MODULE_PARM_DESC(status, "Change pd status.");
+#endif
+
 static void rockchip_pmu_lock(struct rockchip_pm_domain *pd)
 {
 	mutex_lock(&pd->pmu->mutex);
--- a/drivers/video/rockchip/mpp/mpp_iommu.c
+++ b/drivers/video/rockchip/mpp/mpp_iommu.c
@@ -527,7 +527,8 @@ mpp_iommu_probe(struct device *dev)
 		goto err_put_group;
 	}

-	init_rwsem(&info->rw_sem);
+	init_rwsem(&info->rw_sem_self);
+	info->rw_sem = &info->rw_sem_self;
 	spin_lock_init(&info->dev_lock);
 	info->dev = dev;
 	info->pdev = pdev;
--- a/drivers/video/rockchip/mpp/mpp_iommu.h
+++ b/drivers/video/rockchip/mpp/mpp_iommu.h
@@ -81,7 +81,8 @@ struct mpp_rk_iommu {
 struct mpp_dev;

 struct mpp_iommu_info {
-	struct rw_semaphore rw_sem;
+	struct rw_semaphore *rw_sem;
+	struct rw_semaphore rw_sem_self;

 	struct device *dev;
 	struct platform_device *pdev;
@@ -139,7 +140,7 @@ int mpp_iommu_reserve_iova(struct mpp_iommu_info *info, dma_addr_t iova, size_t
 static inline int mpp_iommu_down_read(struct mpp_iommu_info *info)
 {
 	if (info)
-		down_read(&info->rw_sem);
+		down_read(info->rw_sem);

 	return 0;
 }
@@ -147,7 +148,7 @@ static inline int mpp_iommu_down_read(struct mpp_iommu_info *info)
 static inline int mpp_iommu_up_read(struct mpp_iommu_info *info)
 {
 	if (info)
-		up_read(&info->rw_sem);
+		up_read(info->rw_sem);

 	return 0;
 }
@@ -155,7 +156,7 @@ static inline int mpp_iommu_up_read(struct mpp_iommu_info *info)
 static inline int mpp_iommu_down_write(struct mpp_iommu_info *info)
 {
 	if (info)
-		down_write(&info->rw_sem);
+		down_write(info->rw_sem);

 	return 0;
 }
@@ -163,7 +164,7 @@ static inline int mpp_iommu_down_write(struct mpp_iommu_info *info)
 static inline int mpp_iommu_up_write(struct mpp_iommu_info *info)
 {
 	if (info)
-		up_write(&info->rw_sem);
+		up_write(info->rw_sem);

 	return 0;
 }