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ODROID-M1: arch/arm64: add new board Hardkernel's ODROID-M1
Signed-off-by: Dongjin Kim <tobetter@gmail.com> Signed-off-by: Deokgyu Yang <secugyu@gmail.com> Signed-off-by: Steve Jeong <how2soft@gmail.com> Change-Id: Ifbcc33e8e5c3064b3f4cbd3f6a92224346c4f4b3 ODROID-M1: arm64/dts: change i2c2 pinctrl. - Changed the I2C-2 default pinctrl to i2c2m1_xfer. Signed-off-by: Luke Go <sangch.go@gmail.com> Change-Id: Id234f0d73100e98502b86f91b455cacc2fc6847f
This commit is contained in:
Dongjin Kim
committed by
codewalkerster
codewalkerster
parent
f86c4ed133
commit
3705226ed0
@@ -353,4 +353,14 @@ config ARCH_ZYNQMP
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help
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This enables support for Xilinx ZynqMP Family
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config ARCH_ROCKCHIP_ODROID_COMMON
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bool
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config ARCH_ROCKCHIP_ODROIDM1
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bool "Hardkernel's ODROID-M1 Single Board Computer"
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select ARCH_ROCKCHIP_ODROID_COMMON
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help
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This enables support for the board ODROID-M1 of Hardkernel
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which is based on ARMv8 SoC of Rockchip, Inc.
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endmenu # "Platform selection"
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@@ -414,3 +414,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb-v14.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb-v14-dual-cam.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb1-v12.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126bp-evb1-v12-fastboot-emmc.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
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174
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
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174
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
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@@ -0,0 +1,174 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Hardkernel Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3568-odroid.dtsi"
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#include "rk3568-linux.dtsi"
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/ {
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model = "Hardkernel ODROID-M1";
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aliases {
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serial0 = &uart1;
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serial1 = &uart0;
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i2c0 = &i2c3;
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i2c3 = &i2c0;
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};
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pcie30_avdd0v9: pcie30-avdd0v9 {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd0v9";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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vin-supply = <&vcc3v3_sys>;
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};
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pcie30_avdd1v8: pcie30-avdd1v8 {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vcc3v3_pcie: gpio-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <5000>;
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vin-supply = <&dc_12v>;
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};
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};
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&combphy0_us {
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status = "okay";
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};
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&combphy1_usq {
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status = "okay";
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};
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&combphy2_psq {
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status = "okay";
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};
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&gpio0 {
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gpio-line-names =
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/* GPIO0_A */
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"", "", "", "", "", "", "", "",
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/* GPIO0_B */
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"", "", "",
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"PIN_28", /* GPIO0_B3 */
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"PIN_27", /* GPIO0_B4 */
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"PIN_33", /* GPIO0_B5 */
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"PIN_7", /* GPIO0_B6 */
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"",
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/* GPIO0_C */
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"PIN_11", /* GPIO0_C0 */
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"PIN_13", /* GPIO0_C1 */
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"", "", "", "", "", "",
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/* GPIO0_D */
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"", "", "", "", "", "", "", "";
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};
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&gpio1 {
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gpio-line-names =
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/* GPIO1_A */
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"", "", "", "", "", "", "", "",
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/* GPIO1_B */
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"", "", "", "", "", "", "", "",
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/* GPIO1_C */
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"", "", "", "", "", "", "", "",
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/* GPIO1_D */
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"", "", "", "", "", "", "", "";
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};
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&gpio2 {
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gpio-line-names =
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/* GPIO2_A */
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"", "", "", "", "", "", "", "",
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/* GPIO2_B */
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"", "", "", "", "", "", "", "",
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/* GPIO2_C */
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"", "", "", "", "", "", "", "",
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/* GPIO2_D */
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"PIN_21", /* GPIO2_D0 */
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"PIN_19", /* GPIO2_D1 */
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"PIN_24", /* GPIO2_D2 */
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"PIN_23", /* GPIO2_D3 */
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"", "", "", "";
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};
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&gpio3 {
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gpio-line-names =
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/* GPIO3_A */
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"", "", "", "", "", "", "", "",
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/* GPIO3_B */
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"", "",
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"PIN_15", /* GPIO3_B2 */
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"", "",
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"PIN_5", /* GPIO3_B5 */
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"PIN_3", /* GPIO3_B6 */
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"",
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/* GPIO3_C */
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"", "", "", "", "", "",
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"PIN_16", /* GPIO3_C6 */
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"PIN_18", /* GPIO3_C7 */
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/* GPIO3_D */
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"PIN_12", /* GPIO3_D0 */
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"PIN_22", /* GPIO3_D1 */
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"PIN_26", /* GPIO3_D2 */
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"PIN_32", /* GPIO3_D3 */
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"PIN_36", /* GPIO3_D4 */
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"PIN_35", /* GPIO3_D5 */
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"PIN_8", /* GPIO3_D6 */
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"PIN_10"; /* GPIO3_D7 */
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};
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&gpio4 {
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gpio-line-names =
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/* GPIO4_A */
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"", "", "", "", "", "", "", "",
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/* GPIO4_B */
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"", "", "", "", "", "",
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"PIN_31", /* GPIO4_B6 */
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"",
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/* GPIO4_C */
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"",
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"PIN_29", /* GPIO4_C1 */
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"", "", "",
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"", "", "",
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/* GPIO4_D */
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"", "", "", "", "", "", "", "";
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};
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&pcie30phy {
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status = "okay";
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};
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&pcie3x2 {
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reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&sata2 {
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status = "okay";
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};
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&sfc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&fspi_pins>;
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};
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118
arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi
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118
arch/arm64/boot/dts/rockchip/rk3568-odroid.dtsi
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@@ -0,0 +1,118 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Hardkernel Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3568.dtsi"
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#include "rk3568-evb.dtsi"
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/ {
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/delete-node/ adc-keys;
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/delete-node/ nandc@fe330000;
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/delete-node/ sdio-pwrseq;
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/delete-node/ vcc3v3-lcd0-n;
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/delete-node/ vcc3v3-lcd1-n;
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/delete-node/ wireless-bluetooth;
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/delete-node/ wireless-wlan;
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leds: leds {
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power_led: power {
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gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "default-on";
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};
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work_led: work {
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gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&gmac0 {
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phy-mode = "rgmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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tx_delay = <0x4f>;
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rx_delay = <0x2d>;
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phy-handle = <&rgmii_phy0>;
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status = "okay";
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};
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&i2c1 {
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status = "disabled";
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/delete-node/ gt1x@14;
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};
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&i2c2 {
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2m1_xfer>;
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};
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&i2c5 {
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status = "disabled";
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/delete-node/ mxc6655xa@15;
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};
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&mdio0 {
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rgmii_phy0: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&pinctrl {
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/delete-node/ mxc6655xa;
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/delete-node/ touch;
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/delete-node/ wifi-enable-h;
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/delete-node/ wireless-bluetooth;
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fspi {
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fspi_pins: fspi-pins {
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rockchip,pins =
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/* fspi_clk */
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<1 RK_PD0 1 &pcfg_pull_none>,
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/* fspi_cs0n */
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<1 RK_PD3 1 &pcfg_pull_none>,
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/* fspi_d0 */
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<1 RK_PD1 1 &pcfg_pull_none>;
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};
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};
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};
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&pmu_io_domains {
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vccio4-supply = <&vcc_1v8>;
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};
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&rknpu_mmu {
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status = "disabled";
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};
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&rng {
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status = "okay";
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};
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&video_phy0 {
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status = "okay";
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};
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