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clk: rockchip: rk3128: Change SCLK_DDRC to composite

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Change-Id: I6aeae7103c1eaed0b4515d8d11863c4b190b6918
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2019-10-21 16:13:03 +08:00
committed by Tao Huang
parent 649f030b09
commit 37158d1f2b
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk-rk3128.c
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@@ -212,9 +212,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2),
COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0,
RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
ROCKCHIP_DDRCLK_SIP_V2),
FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
/* PD_CORE */