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ODROID-XU4: SPI1 clock setup

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Change-Id: I0d9ec6040409685d2d94baa9172b043c9625f079
This commit is contained in:
charles.park
2017-01-17 14:38:59 +09:00
parent 15285272e9
commit 38949a9e60
3 changed files with 12 additions and 3 deletions
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5
arch/arm/boot/dts/exynos5422-odroidxu4.dts
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@@ -55,6 +55,11 @@
&spi_1 {
status = "okay";
assigned-clocks = <&clock CLK_MOUT_SPI1>, <&clock CLK_DOUT_SPI1>;
assigned-clock-parents = <&clock CLK_MOUT_DPLL>;
assigned-clock-rates = <0>, <80000000>;
samsung,spi-src-clk = <0>;
num-cs = <2>;
cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>, <&gpx2 1 GPIO_ACTIVE_HIGH>;

6
drivers/clk/samsung/clk-exynos5420.c Normal file → Executable file
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@@ -704,7 +704,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
MUX(CLK_MOUT_DPLL, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
@@ -788,7 +788,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
MUX(CLK_MOUT_SPI1, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
/* ISP Block */
@@ -899,7 +899,7 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
/* SPI */
DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
DIV(CLK_DOUT_SPI1, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
/* Mfc Block */

4
include/dt-bindings/clock/exynos5420.h Normal file → Executable file
View File

@@ -218,6 +218,10 @@
#define CLK_MOUT_BPLL 655
#define CLK_MOUT_MX_MSPLL_CCORE 656
#define CLK_MOUT_DPLL 700
#define CLK_MOUT_SPI1 701
#define CLK_DOUT_SPI1 702
/* divider clocks */
#define CLK_DOUT_PIXEL 768
#define CLK_DOUT_ACLK400_WCORE 769