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spi: rockchip: Set rx_fifo interrupt waterline base on transfer item

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Change-Id: Ia141ce99b14f8728302535d0748af66d597a2fdc
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2020-11-20 12:53:21 +08:00
committed by Tao Huang
parent 9dc5ea5543
commit 3a6ad2d61b
1 changed files with 2 additions and 2 deletions
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4
drivers/spi/spi-rockchip.c
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@@ -569,8 +569,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs,
* interrupt exactly when the fifo is full doesn't seem to work,
* so we need the strict inequality here
*/
if (xfer->len < rs->fifo_len)
writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
if ((xfer->len / rs->n_bytes) < rs->fifo_len)
writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
else
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);