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phy: rockchip: naneng-combphy: Fix support for pipe clock settings
pipe clock settings were done before PCIe's and SATA's catch-all pipe settings. So it would be covered by con1_for_pcie and con1_for_sata. Fix this by moving pipe clock settings to the end. Change-Id: I19a8943b6a99d8e4ef198345ec3f62bdac491c58 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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@@ -320,34 +320,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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return -EINVAL;
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}
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rate = clk_get_rate(refclk);
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switch (rate) {
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case 24000000:
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if (priv->mode == PHY_TYPE_USB3) {
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/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
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val = readl(priv->mmio + (0x0e << 2));
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val &= ~GENMASK(7, 6);
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val |= 0x01 << 6;
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writel(val, priv->mmio + (0x0e << 2));
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val = readl(priv->mmio + (0x0f << 2));
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val &= ~GENMASK(7, 0);
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val |= 0x5f;
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writel(val, priv->mmio + (0x0f << 2));
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}
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break;
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case 25000000:
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param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
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break;
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case 100000000:
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param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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break;
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default:
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dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
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return -EINVAL;
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}
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switch (priv->mode) {
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case PHY_TYPE_PCIE:
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param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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@@ -397,6 +369,34 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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return -EINVAL;
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}
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rate = clk_get_rate(refclk);
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switch (rate) {
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case 24000000:
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if (priv->mode == PHY_TYPE_USB3) {
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/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
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val = readl(priv->mmio + (0x0e << 2));
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val &= ~GENMASK(7, 6);
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val |= 0x01 << 6;
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writel(val, priv->mmio + (0x0e << 2));
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val = readl(priv->mmio + (0x0f << 2));
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val &= ~GENMASK(7, 0);
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val |= 0x5f;
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writel(val, priv->mmio + (0x0f << 2));
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}
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break;
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case 25000000:
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param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
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break;
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case 100000000:
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param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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break;
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default:
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dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
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return -EINVAL;
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}
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return 0;
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}
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