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phy: rockchip: naneng-combphy: modify SSC config for SATA

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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Icdb2079028df1edb8973608ad08a51113e1c9ce8
This commit is contained in:
Yifeng Zhao
2021-03-15 11:32:31 +08:00
committed by Tao Huang
parent 0bf3a98dc9
commit 3e6cf0d71a
1 changed files with 7 additions and 2 deletions
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9
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -505,7 +505,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (rate) {
case 24000000:
if (priv->mode == PHY_TYPE_USB3) {
if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
val = readl(priv->mmio + (0x0e << 2));
val &= ~GENMASK(7, 6);
@@ -540,7 +540,12 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
writel(0x32, priv->mmio + (0x11 << 2));
writel(0xf0, priv->mmio + (0xa << 2));
} else if (priv->mode == PHY_TYPE_SATA) {
/* downward spread spectrum +500ppm */
val = readl(priv->mmio + (0x1f << 2));
val &= ~GENMASK(7, 4);
val |= 0x50;
writel(val, priv->mmio + (0x1f << 2));
}
break;
default: