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hdmirx: power down the phy at suspend for tl1 [1/1]

Browse Source 
PD#TV-1212

Problem:
the power comsuption is too high for hdmirx

Solution:
1.power down the phy at suspend
2.power on the phy at resume

Verify:
x301

Change-Id: I8920a6b38197109d424d225c4b31f5170b56ca08
Signed-off-by: hongmin hua <hongmin.hua@amlogic.com>
This commit is contained in:
Hongmin Hua
2018-11-28 14:24:16 +08:00
committed by Jianxin Pan
parent 93cc0f07ee
commit 3ed3bbde07
3 changed files with 49 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -34,7 +34,7 @@
#include "hdmi_rx_edid.h"
#define RX_VER0 "ver.2018-11-8"
#define RX_VER0 "ver.2018-11-28"
/*
*
*

65
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -386,6 +386,18 @@ unsigned int rd_reg_hhi(unsigned int offset)
return rd_reg(MAP_ADDR_MODULE_HIU, addr);
}
/*
* rd_reg_hhi_bits - read specfied bits of HHI reg
* @addr: register address
* @mask: bits mask
*
* return masked bits of register value
*/
unsigned int rd_reg_hhi_bits(unsigned int offset, unsigned int mask)
{
return rx_get_bits(rd_reg_hhi(offset), mask);
}
/*
* wr_reg_hhi
* @offset: offset address of hhi physical addr
@@ -398,6 +410,17 @@ void wr_reg_hhi(unsigned int offset, unsigned int val)
wr_reg(MAP_ADDR_MODULE_HIU, addr, val);
}
/*
* wr_reg_hhi_bits
* @offset: offset address of hhi physical addr
* @mask: modify bits mask
* @val: value being written
*/
void wr_reg_hhi_bits(unsigned int offset, unsigned int mask, unsigned int val)
{
wr_reg_hhi(offset, rx_set_bits(rd_reg_hhi(offset), mask, val));
}
/*
* rd_reg - regisger read
* @module: module index of the reg_map table
@@ -665,8 +688,11 @@ unsigned int rx_set_hdcp14_secure_key(void)
*/
void hdmirx_phy_pddq(unsigned int enable)
{
hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL,
MSK(1, 1), enable);
if (rx.chip_id == CHIP_ID_TL1)
wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL2, _BIT(1), enable);
else
hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL,
MSK(1, 1), enable);
}
/*
@@ -3532,28 +3558,27 @@ unsigned int aml_phy_tmds_valid(void)
void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2)
{
/* for tl1 no SW eq */
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
/* ... */
} else {
/* set rxsense pulse */
hdmirx_phy_pddq(1);
mdelay(t1);
hdmirx_phy_pddq(0);
mdelay(t2);
}
/* set rxsense pulse */
hdmirx_phy_pddq(1);
mdelay(t1);
hdmirx_phy_pddq(0);
mdelay(t2);
}
void rx_phy_power_on(unsigned int onoff)
{
if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) {
/* ... */
} else {
if (onoff)
hdmirx_phy_pddq(0);
else
hdmirx_phy_pddq(1);
if (onoff)
hdmirx_phy_pddq(0);
else
hdmirx_phy_pddq(1);
if (rx.chip_id == CHIP_ID_TL1) {
/*the enable of these regs are in phy init*/
if (onoff == 0) {
wr_reg_hhi_bits(HHI_HDMIRX_APLL_CNTL0, _BIT(28), onoff);
/*close termination 3.3v*/
wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL0,
MSK(3, 0), onoff);
}
}
}

3
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
View File

@@ -1103,7 +1103,10 @@ extern int ignore_sscp_charerr;
extern int ignore_sscp_tmds;
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
extern void wr_reg_hhi_bits(unsigned int offset, unsigned int mask,
unsigned int val);
extern unsigned int rd_reg_hhi(unsigned int offset);
extern unsigned int rd_reg_hhi_bits(unsigned int offset, unsigned int mask);
extern unsigned int rd_reg(enum map_addr_module_e module,
unsigned int reg_addr);
extern void wr_reg(enum map_addr_module_e module,