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video: rockchip: rga3: fix the memory arrangement of ARGB5551/4444
1. Fixed swap config of ARGB/ABGR 5551/4444. 2. RGA2 removes unsupported RGBA/BGRA 5551/4444 input. Update driver version to 1.3.2 Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com> Change-Id: I3d2300f07282a256e2950e3400e9a52e9702164d
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@@ -87,7 +87,7 @@
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#define DRIVER_MAJOR_VERISON 1
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#define DRIVER_MINOR_VERSION 3
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#define DRIVER_REVISION_VERSION 1
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#define DRIVER_REVISION_VERSION 2
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#define DRIVER_PATCH_VERSION
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#define DRIVER_VERSION (STR(DRIVER_MAJOR_VERISON) "." STR(DRIVER_MINOR_VERSION) \
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@@ -425,30 +425,12 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg)
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pixel_width = 2;
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msg->src_trans_mode &= 0x07;
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break;
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case RGA_FORMAT_RGBA_5551:
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src0_format = 0x5;
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pixel_width = 2;
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break;
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case RGA_FORMAT_RGBA_4444:
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src0_format = 0x6;
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pixel_width = 2;
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break;
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case RGA_FORMAT_BGR_565:
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src0_format = 0x4;
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pixel_width = 2;
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msg->src_trans_mode &= 0x07;
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src0_rb_swp = 0x1;
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break;
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case RGA_FORMAT_BGRA_5551:
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src0_format = 0x5;
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pixel_width = 2;
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src0_rb_swp = 0x1;
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break;
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case RGA_FORMAT_BGRA_4444:
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src0_format = 0x6;
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pixel_width = 2;
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src0_rb_swp = 0x1;
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break;
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/* ARGB */
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/*
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@@ -482,23 +464,19 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg)
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case RGA_FORMAT_ARGB_5551:
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src0_format = 0x5;
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pixel_width = 2;
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src0_alpha_swp = 1;
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break;
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case RGA_FORMAT_ABGR_5551:
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src0_format = 0x5;
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pixel_width = 2;
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src0_alpha_swp = 1;
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src0_rb_swp = 0x1;
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break;
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case RGA_FORMAT_ARGB_4444:
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src0_format = 0x6;
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pixel_width = 2;
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src0_alpha_swp = 1;
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break;
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case RGA_FORMAT_ABGR_4444:
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src0_format = 0x6;
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pixel_width = 2;
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src0_alpha_swp = 1;
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src0_rb_swp = 0x1;
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break;
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@@ -947,29 +925,11 @@ static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
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src1_format = 0x4;
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spw = 2;
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break;
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case RGA_FORMAT_RGBA_5551:
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src1_format = 0x5;
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spw = 2;
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break;
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case RGA_FORMAT_RGBA_4444:
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src1_format = 0x6;
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spw = 2;
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break;
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case RGA_FORMAT_BGR_565:
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src1_format = 0x4;
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spw = 2;
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src1_rb_swp = 0x1;
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break;
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case RGA_FORMAT_BGRA_5551:
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src1_format = 0x5;
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spw = 2;
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src1_rb_swp = 0x1;
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break;
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case RGA_FORMAT_BGRA_4444:
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src1_format = 0x6;
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spw = 2;
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src1_rb_swp = 0x1;
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break;
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/* ARGB */
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case RGA_FORMAT_ARGB_8888:
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@@ -997,23 +957,19 @@ static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
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case RGA_FORMAT_ARGB_5551:
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src1_format = 0x5;
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spw = 2;
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src1_alpha_swp = 1;
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break;
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case RGA_FORMAT_ABGR_5551:
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src1_format = 0x5;
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spw = 2;
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src1_alpha_swp = 1;
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src1_rb_swp = 0x1;
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break;
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case RGA_FORMAT_ARGB_4444:
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src1_format = 0x6;
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spw = 2;
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src1_alpha_swp = 1;
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break;
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case RGA_FORMAT_ABGR_4444:
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src1_format = 0x6;
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spw = 2;
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src1_alpha_swp = 1;
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src1_rb_swp = 0x1;
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break;
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case RGA_FORMAT_RGBA_2BPP:
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@@ -109,10 +109,6 @@ const uint32_t rga2e_input_raster_format[] = {
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RGA_FORMAT_YCbCr_422_SP_10B,
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RGA_FORMAT_YCrCb_422_SP_10B,
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RGA_FORMAT_YCbCr_400,
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RGA_FORMAT_RGBA_5551,
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RGA_FORMAT_BGRA_5551,
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RGA_FORMAT_RGBA_4444,
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RGA_FORMAT_BGRA_4444,
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RGA_FORMAT_XRGB_8888,
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RGA_FORMAT_XBGR_8888,
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RGA_FORMAT_BPP1,
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@@ -158,10 +154,6 @@ const uint32_t rga2e_output_raster_format[] = {
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RGA_FORMAT_YCrCb_422_SP_10B,
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RGA_FORMAT_Y4,
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RGA_FORMAT_YCbCr_400,
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RGA_FORMAT_RGBA_5551,
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RGA_FORMAT_BGRA_5551,
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RGA_FORMAT_RGBA_4444,
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RGA_FORMAT_BGRA_4444,
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RGA_FORMAT_XRGB_8888,
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RGA_FORMAT_XBGR_8888,
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RGA_FORMAT_ARGB_8888,
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@@ -198,10 +190,6 @@ const uint32_t rga2p_input_raster_format[] = {
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RGA_FORMAT_YCbCr_422_SP_10B,
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RGA_FORMAT_YCrCb_422_SP_10B,
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RGA_FORMAT_YCbCr_400,
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RGA_FORMAT_RGBA_5551,
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RGA_FORMAT_BGRA_5551,
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RGA_FORMAT_RGBA_4444,
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RGA_FORMAT_BGRA_4444,
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RGA_FORMAT_XRGB_8888,
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RGA_FORMAT_XBGR_8888,
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RGA_FORMAT_BPP1,
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@@ -229,12 +217,8 @@ const uint32_t rga2p_input1_raster_format[] = {
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RGA_FORMAT_XBGR_8888,
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RGA_FORMAT_ARGB_8888,
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RGA_FORMAT_ABGR_8888,
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RGA_FORMAT_RGBA_5551,
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RGA_FORMAT_BGRA_5551,
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RGA_FORMAT_ARGB_5551,
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RGA_FORMAT_ABGR_5551,
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RGA_FORMAT_RGBA_4444,
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RGA_FORMAT_BGRA_4444,
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RGA_FORMAT_ARGB_4444,
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RGA_FORMAT_ABGR_4444,
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RGA_FORMAT_RGB_888,
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