video: rockchip: rga3: fix the memory arrangement of ARGB5551/4444

1. Fixed swap config of ARGB/ABGR 5551/4444.
2. RGA2 removes unsupported RGBA/BGRA 5551/4444 input.

Update driver version to 1.3.2

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I3d2300f07282a256e2950e3400e9a52e9702164d
This commit is contained in:
Yu Qiaowei
2024-03-05 10:49:00 +08:00
committed by Tao Huang
parent af4fb1ab5d
commit 400d274169
3 changed files with 1 additions and 61 deletions

View File

@@ -87,7 +87,7 @@
#define DRIVER_MAJOR_VERISON 1
#define DRIVER_MINOR_VERSION 3
#define DRIVER_REVISION_VERSION 1
#define DRIVER_REVISION_VERSION 2
#define DRIVER_PATCH_VERSION
#define DRIVER_VERSION (STR(DRIVER_MAJOR_VERISON) "." STR(DRIVER_MINOR_VERSION) \

View File

@@ -425,30 +425,12 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg)
pixel_width = 2;
msg->src_trans_mode &= 0x07;
break;
case RGA_FORMAT_RGBA_5551:
src0_format = 0x5;
pixel_width = 2;
break;
case RGA_FORMAT_RGBA_4444:
src0_format = 0x6;
pixel_width = 2;
break;
case RGA_FORMAT_BGR_565:
src0_format = 0x4;
pixel_width = 2;
msg->src_trans_mode &= 0x07;
src0_rb_swp = 0x1;
break;
case RGA_FORMAT_BGRA_5551:
src0_format = 0x5;
pixel_width = 2;
src0_rb_swp = 0x1;
break;
case RGA_FORMAT_BGRA_4444:
src0_format = 0x6;
pixel_width = 2;
src0_rb_swp = 0x1;
break;
/* ARGB */
/*
@@ -482,23 +464,19 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg)
case RGA_FORMAT_ARGB_5551:
src0_format = 0x5;
pixel_width = 2;
src0_alpha_swp = 1;
break;
case RGA_FORMAT_ABGR_5551:
src0_format = 0x5;
pixel_width = 2;
src0_alpha_swp = 1;
src0_rb_swp = 0x1;
break;
case RGA_FORMAT_ARGB_4444:
src0_format = 0x6;
pixel_width = 2;
src0_alpha_swp = 1;
break;
case RGA_FORMAT_ABGR_4444:
src0_format = 0x6;
pixel_width = 2;
src0_alpha_swp = 1;
src0_rb_swp = 0x1;
break;
@@ -947,29 +925,11 @@ static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
src1_format = 0x4;
spw = 2;
break;
case RGA_FORMAT_RGBA_5551:
src1_format = 0x5;
spw = 2;
break;
case RGA_FORMAT_RGBA_4444:
src1_format = 0x6;
spw = 2;
break;
case RGA_FORMAT_BGR_565:
src1_format = 0x4;
spw = 2;
src1_rb_swp = 0x1;
break;
case RGA_FORMAT_BGRA_5551:
src1_format = 0x5;
spw = 2;
src1_rb_swp = 0x1;
break;
case RGA_FORMAT_BGRA_4444:
src1_format = 0x6;
spw = 2;
src1_rb_swp = 0x1;
break;
/* ARGB */
case RGA_FORMAT_ARGB_8888:
@@ -997,23 +957,19 @@ static void RGA2_set_reg_dst_info(u8 *base, struct rga2_req *msg)
case RGA_FORMAT_ARGB_5551:
src1_format = 0x5;
spw = 2;
src1_alpha_swp = 1;
break;
case RGA_FORMAT_ABGR_5551:
src1_format = 0x5;
spw = 2;
src1_alpha_swp = 1;
src1_rb_swp = 0x1;
break;
case RGA_FORMAT_ARGB_4444:
src1_format = 0x6;
spw = 2;
src1_alpha_swp = 1;
break;
case RGA_FORMAT_ABGR_4444:
src1_format = 0x6;
spw = 2;
src1_alpha_swp = 1;
src1_rb_swp = 0x1;
break;
case RGA_FORMAT_RGBA_2BPP:

View File

@@ -109,10 +109,6 @@ const uint32_t rga2e_input_raster_format[] = {
RGA_FORMAT_YCbCr_422_SP_10B,
RGA_FORMAT_YCrCb_422_SP_10B,
RGA_FORMAT_YCbCr_400,
RGA_FORMAT_RGBA_5551,
RGA_FORMAT_BGRA_5551,
RGA_FORMAT_RGBA_4444,
RGA_FORMAT_BGRA_4444,
RGA_FORMAT_XRGB_8888,
RGA_FORMAT_XBGR_8888,
RGA_FORMAT_BPP1,
@@ -158,10 +154,6 @@ const uint32_t rga2e_output_raster_format[] = {
RGA_FORMAT_YCrCb_422_SP_10B,
RGA_FORMAT_Y4,
RGA_FORMAT_YCbCr_400,
RGA_FORMAT_RGBA_5551,
RGA_FORMAT_BGRA_5551,
RGA_FORMAT_RGBA_4444,
RGA_FORMAT_BGRA_4444,
RGA_FORMAT_XRGB_8888,
RGA_FORMAT_XBGR_8888,
RGA_FORMAT_ARGB_8888,
@@ -198,10 +190,6 @@ const uint32_t rga2p_input_raster_format[] = {
RGA_FORMAT_YCbCr_422_SP_10B,
RGA_FORMAT_YCrCb_422_SP_10B,
RGA_FORMAT_YCbCr_400,
RGA_FORMAT_RGBA_5551,
RGA_FORMAT_BGRA_5551,
RGA_FORMAT_RGBA_4444,
RGA_FORMAT_BGRA_4444,
RGA_FORMAT_XRGB_8888,
RGA_FORMAT_XBGR_8888,
RGA_FORMAT_BPP1,
@@ -229,12 +217,8 @@ const uint32_t rga2p_input1_raster_format[] = {
RGA_FORMAT_XBGR_8888,
RGA_FORMAT_ARGB_8888,
RGA_FORMAT_ABGR_8888,
RGA_FORMAT_RGBA_5551,
RGA_FORMAT_BGRA_5551,
RGA_FORMAT_ARGB_5551,
RGA_FORMAT_ABGR_5551,
RGA_FORMAT_RGBA_4444,
RGA_FORMAT_BGRA_4444,
RGA_FORMAT_ARGB_4444,
RGA_FORMAT_ABGR_4444,
RGA_FORMAT_RGB_888,