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clk: rockchip: rk3128: fix up the hclk_vio clk description

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set hclk_vio_niu as critical clock.

Change-Id: Ib9e182ac93038df34eadae502fc18df5c0854ef9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-10-20 11:08:30 +08:00
committed by Tao Huang
parent 987f984d07
commit 4124fe9936
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk-rk3128.c
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@@ -274,8 +274,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,
RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
FACTOR_GATE(HCLK_VIO, "hclk_vio", "aclk_vio0", 0, 1, 4,
RK2928_CLKGATE_CON(0), 11, GFLAGS),
/* PD_PERI */
@@ -317,7 +316,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(10), 1, GFLAGS),
GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
RK2928_CLKGATE_CON(10), 2, GFLAGS),
GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", 0,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
@@ -576,6 +575,7 @@ static const char *const rk3128_critical_clocks[] __initconst = {
"pclk_peri",
"pclk_pmu",
"sclk_timer5",
"hclk_vio_niu",
};
static void __iomem *rk312x_reg_base;