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drm/rockchp: dw-dp: enable video stream fifo overflow irq

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Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I73e33d60db8886b150c390b387ba360bafbc0b72
This commit is contained in:
Zhang Yubing
2022-03-12 11:55:15 +08:00
committed by Tao Huang
parent b358a51aef
commit 41fe643f8c
1 changed files with 35 additions and 0 deletions
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35
drivers/gpu/drm/rockchip/dw-dp.c
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@@ -171,6 +171,9 @@
#define DPTX_AUX_DATA3 0x0b14
#define DPTX_GENERAL_INTERRUPT 0x0d00
#define VIDEO_FIFO_OVERFLOW_STREAM3 BIT(26)
#define VIDEO_FIFO_OVERFLOW_STREAM2 BIT(20)
#define VIDEO_FIFO_OVERFLOW_STREAM1 BIT(14)
#define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6)
#define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5)
#define SDP_EVENT_STREAM0 BIT(4)
@@ -2900,6 +2903,14 @@ static void dw_dp_init(struct dw_dp *dp)
dw_dp_hpd_init(dp);
dw_dp_aux_init(dp);
regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE,
VIDEO_FIFO_OVERFLOW_STREAM0 | VIDEO_FIFO_OVERFLOW_STREAM1 |
VIDEO_FIFO_OVERFLOW_STREAM2 | VIDEO_FIFO_OVERFLOW_STREAM3,
FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM0, 1) |
FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM1, 1) |
FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM2, 1) |
FIELD_PREP(VIDEO_FIFO_OVERFLOW_STREAM3, 1));
}
static void dw_dp_encoder_enable(struct drm_encoder *encoder)
@@ -5084,6 +5095,30 @@ static irqreturn_t dw_dp_irq_handler(int irq, void *data)
if (value & HDCP_EVENT)
dw_dp_handle_hdcp_event(dp);
if (value & VIDEO_FIFO_OVERFLOW_STREAM0) {
dev_err_ratelimited(dp->dev, "video fifo overflow stream0\n");
regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT,
VIDEO_FIFO_OVERFLOW_STREAM0);
}
if (value & VIDEO_FIFO_OVERFLOW_STREAM1) {
dev_err_ratelimited(dp->dev, "video fifo overflow stream1\n");
regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT,
VIDEO_FIFO_OVERFLOW_STREAM1);
}
if (value & VIDEO_FIFO_OVERFLOW_STREAM2) {
dev_err_ratelimited(dp->dev, "video fifo overflow stream2\n");
regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT,
VIDEO_FIFO_OVERFLOW_STREAM2);
}
if (value & VIDEO_FIFO_OVERFLOW_STREAM3) {
dev_err_ratelimited(dp->dev, "video fifo overflow stream3\n");
regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT,
VIDEO_FIFO_OVERFLOW_STREAM3);
}
return IRQ_HANDLED;
}