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pwm: rockchip: add one period delay before disabling the dclk

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For pwm v4, the disable operation, which sets polarity
to inactive state, will not take effect until the end
of current period.

Change-Id: Ie632b69d06495d96b79b9c743e69175cd5c175ed
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2024-03-04 19:53:21 +08:00
committed by Tao Huang
parent c260cfd73c
commit 42e759004f
1 changed files with 7 additions and 1 deletions
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8
drivers/pwm/pwm-rockchip.c
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@@ -783,6 +783,8 @@ static void rockchip_pwm_config_v4(struct pwm_chip *chip, struct pwm_device *pwm
static int rockchip_pwm_enable_v4(struct pwm_chip *chip, struct pwm_device *pwm, bool enable)
{
struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
struct pwm_state curstate;
unsigned long delay_us;
int ret;
if (enable) {
@@ -793,8 +795,12 @@ static int rockchip_pwm_enable_v4(struct pwm_chip *chip, struct pwm_device *pwm,
writel_relaxed(PWM_EN(enable) | PWM_CLK_EN(enable), pc->base + ENABLE);
if (!enable)
if (!enable) {
pwm_get_state(pwm, &curstate);
delay_us = DIV_ROUND_UP_ULL(curstate.period, NSEC_PER_USEC);
fsleep(delay_us);
clk_disable(pc->clk);
}
return 0;
}