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hdmirx: add rx phy tdr enable control [1/1]

Browse Source 
PD#SWPL-13433

Problem:
Need to add a option in dts to select tdr on or off;

Solution:
add a option in dts to select tdr on or off;

Verify:
tl1

Change-Id: Ibf5688fcf50672677369452f7dd6e702094eac5e
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
This commit is contained in:
yicheng shen
2019-11-18 15:02:52 +08:00
committed by Luke Go
parent 4663947b42
commit 462ca5f34d
28 changed files with 81 additions and 14874 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1669
arch/arm/boot/dts/amlogic/sm1_s905d3_ac200.dts
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File diff suppressed because it is too large Load Diff

1942
arch/arm/boot/dts/amlogic/sm1_s905d3_ac200_drm_buildroot.dts
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File diff suppressed because it is too large Load Diff

1965
arch/arm/boot/dts/amlogic/sm1_s905d3_ac202.dts
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File diff suppressed because it is too large Load Diff

1884
arch/arm/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
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File diff suppressed because it is too large Load Diff

5
arch/arm/boot/dts/amlogic/tl1_pxp.dts
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@@ -401,7 +401,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <0>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x10>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
View File

@@ -627,7 +627,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <0>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x10>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
View File

@@ -879,7 +879,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
View File

@@ -874,7 +874,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -559,7 +559,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <0>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x10>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -814,7 +814,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -786,7 +786,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -815,7 +815,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -787,7 +787,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

1659
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
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File diff suppressed because it is too large Load Diff

1929
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200_drm_buildroot.dts
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File diff suppressed because it is too large Load Diff

1891
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202.dts
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File diff suppressed because it is too large Load Diff

1914
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
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File diff suppressed because it is too large Load Diff

5
arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
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@@ -995,7 +995,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
View File

@@ -875,7 +875,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
View File

@@ -869,7 +869,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm64/boot/dts/amlogic/tm2_pxp.dts
View File

@@ -559,7 +559,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <0>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x10>;
interrupts = <0 41 1>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -809,7 +809,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
View File

@@ -785,7 +785,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

5
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -786,7 +786,10 @@
pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
&hdmirx_c_mux>;
repeat = <0>;
term_lvl = <1>;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
term_lvl = <0x11>;
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
<&clkc CLKID_HDMIRX_CFG_COMP>,

3
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
View File

@@ -2454,7 +2454,8 @@ static int hdmirx_probe(struct platform_device *pdev)
rx_emp_resource_allocate(&(pdev->dev));
aml_phy_get_trim_val();
hdmirx_hw_probe();
term_cal_en = (!is_ft_trim_done());
if ((rx.chip_id >= CHIP_ID_TL1) && phy_tdr_en)
term_cal_en = (!is_ft_trim_done());
hdmirx_init_params();
hdmirx_switch_pinmux(&(pdev->dev));
#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND

17
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -109,7 +109,11 @@ int scdc_force_en = 1;
bool hdcp_hpd_ctrl_en;
int eq_dbg_lvl;
u32 phy_trim_val;
/* bit 4: tdr enable bit
* bit [3:0]: tdr level control
*/
int phy_term_lel;
bool phy_tdr_en;
/*------------------------variable define end------------------------------*/
@@ -3675,13 +3679,20 @@ void aml_phy_init_1(void)
bool is_ft_trim_done(void)
{
return phy_trim_val & 0x1;
int ret = phy_trim_val & 0x1;
rx_pr("ft trim=%d\n", ret);
return ret;
}
void aml_phy_get_trim_val(void)
{
u32 data32;
if (rx.chip_id < CHIP_ID_TL1)
return;
phy_tdr_en = (phy_term_lel >> 4) & 0x1;
phy_term_lel = phy_term_lel & 0xf;
phy_trim_val = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1);
data32 = (phy_trim_val >> 12) & 0x3ff;
data32 = (~((~data32) << phy_term_lel) | (1 << phy_term_lel));
@@ -3716,14 +3727,12 @@ void aml_phy_init(void)
udelay(2);
data32 = phy_misci[idx][1];
if (idx < phy_frq_band_5) {
if ((idx < phy_frq_band_5) && phy_tdr_en) {
if (term_cal_en) {
data32 = (((data32 & (~(0x3ff << 12))) |
(term_cal_val << 12)) | (1 << 22));
rx_pr("man term mode\n");
} else {
data32 = phy_trim_val;
rx_pr("ft trim mode\n");
}
}
wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, data32);

1
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
View File

@@ -1124,6 +1124,7 @@ extern int scdc_force_en;
extern bool hdcp_hpd_ctrl_en;
extern int eq_dbg_lvl;
extern int phy_term_lel;
extern bool phy_tdr_en;
extern void rx_get_best_eq_setting(void);
extern void wr_reg_hhi(unsigned int offset, unsigned int val);

1
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -2931,6 +2931,7 @@ int hdmirx_debug(const char *buf, int size)
rx_pr("Hdmirx version0: %s\n", RX_VER0);
rx_pr("Hdmirx version1: %s\n", RX_VER1);
rx_pr("Hdmirx version2: %s\n", RX_VER2);
rx_pr("Hdmirx version2: %s\n", "ver.2019/11/18");
rx_pr("------------------\n");
} else if (strncmp(input[0], "port0", 5) == 0) {
hdmirx_open_port(TVIN_PORT_HDMI0);