hdmirx: add phy TDR function [1/1]

PD#SWPL-16740 Problem: Add phy TDR function to get the best setting. Solution: Add phy TDR function to get the best setting. Verify: TL1 Change-Id: Id2652cbf8cc9f3bf2a7cf79edc110333a13fd67d Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
2026-06-08 20:07:46 +09:00 · 2019-09-16 06:55:53 -04:00
parent 58788b839b
commit 4663947b42
20 changed files with 118 additions and 3 deletions
--- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts
@@ -401,6 +401,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <0>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
@@ -627,6 +627,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <0>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
@@ -879,6 +879,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
@@ -874,6 +874,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tm2_pxp.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_pxp.dts
@@ -559,6 +559,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <0>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
@@ -814,6 +814,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
@@ -786,6 +786,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
@@ -815,6 +815,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
@@ -787,6 +787,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
@@ -995,6 +995,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
@@ -875,6 +875,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
@@ -869,6 +869,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm64/boot/dts/amlogic/tm2_pxp.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_pxp.dts
@@ -559,6 +559,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <0>;
 		interrupts = <0 41 1>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
@@ -809,6 +809,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
@@ -785,6 +785,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
@@ -786,6 +786,7 @@
 		pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux
 			&hdmirx_c_mux>;
 		repeat = <0>;
+		term_lvl = <1>;
 		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clkc CLKID_HDMIRX_MODET_COMP>,
 			   <&clkc CLKID_HDMIRX_CFG_COMP>,
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
@@ -2375,6 +2375,14 @@ static int hdmirx_probe(struct platform_device *pdev)
 			clk_prepare_enable(hdevp->axi_clk);
 			clk_rate = clk_get_rate(hdevp->axi_clk);
 		}
+		/* */
+		ret = of_property_read_u32(pdev->dev.of_node,
+					   "term_lvl",
+							&phy_term_lel);
+		if (ret) {
+			rx_pr("term_lvl not found.\n");
+			phy_term_lel = 0;
+		}
 	} else {
 		hdevp->audmeas_clk = clk_get(&pdev->dev, "hdmirx_audmeas_clk");
 		if (IS_ERR(hdevp->audmeas_clk))
@@ -2444,7 +2452,9 @@ static int hdmirx_probe(struct platform_device *pdev)
 	if (ret != 0)
 		rx_pr("warning: no rev cmd mem\n");
 	rx_emp_resource_allocate(&(pdev->dev));
+	aml_phy_get_trim_val();
 	hdmirx_hw_probe();
+	term_cal_en = (!is_ft_trim_done());
 	hdmirx_init_params();
 	hdmirx_switch_pinmux(&(pdev->dev));
 #ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
@@ -101,11 +101,15 @@ int eq_try_cnt = 20;
 int pll_rst_max = 5;
 /* cdr lock threshold */
 int cdr_lock_level;
+u32 term_cal_val;
+bool term_cal_en;
 int clock_lock_th = 2;
 int scdc_force_en = 1;
 /* for hdcp_hpd debug, disable by default */
 bool hdcp_hpd_ctrl_en;
 int eq_dbg_lvl;
+u32 phy_trim_val;
+int phy_term_lel;

 /*------------------------variable define end------------------------------*/

@@ -3669,6 +3673,21 @@ void aml_phy_init_1(void)
 	wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32);/*398*/
 }

+bool is_ft_trim_done(void)
+{
+	return  phy_trim_val & 0x1;
+}
+
+void aml_phy_get_trim_val(void)
+{
+	u32 data32;
+
+	phy_trim_val = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1);
+	data32 = (phy_trim_val >> 12) & 0x3ff;
+	data32 = (~((~data32) << phy_term_lel) | (1 << phy_term_lel));
+	phy_trim_val = ((phy_trim_val & (~(0x3ff << 12)))
+		| (data32 << 12));
+}
 void aml_phy_init(void)
 {
 	uint32_t idx = rx.phy.phy_bw;
@@ -3697,8 +3716,17 @@ void aml_phy_init(void)
 	udelay(2);

 	data32 = phy_misci[idx][1];
+	if (idx < phy_frq_band_5) {
+		if (term_cal_en) {
+			data32 = (((data32 & (~(0x3ff << 12))) |
+				(term_cal_val << 12)) | (1 << 22));
+			rx_pr("man term mode\n");
+		} else {
+			data32 = phy_trim_val;
+			rx_pr("ft trim mode\n");
+		}
+	}
 	wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, data32);
-
 	wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, phy_misci[idx][2]);

 	/* reset and select data port */
@@ -4419,3 +4447,51 @@ void rx_get_audio_N_CTS(uint32_t *N, uint32_t *CTS)
 	*CTS = hdmirx_rd_top(TOP_ACR_CTS_STAT);
 }

+/* termination calibration */
+void rx_phy_rt_cal(void)
+{
+	int i = 0, j = 0;
+	u32 x_val[100][2];
+	u32 temp;
+	int val_cnt = 1;
+
+	rx_pr("360=0x%x\n", rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1));
+	for (; i < 100; i++) {
+		wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL0, MISCI_COMMON_RST, 0);
+		wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL0, MISCI_COMMON_RST, 1);
+		udelay(1);
+		temp = (rd_reg_hhi(HHI_HDMIRX_PHY_MISC_STAT) >> 1) & 0x3ff;
+		rx_pr("temp=%x\n", temp);
+		if (i == 0) {
+			x_val[0][0] = temp;
+			x_val[0][1] = 1;
+		}
+
+		for (; j < i; j++) {
+			rx_pr("j=%d\n", j);
+			if (temp == x_val[j][0]) {
+				x_val[j][1]	+= 1;
+				rx_pr("++,val=%x\n", x_val[j][0]);
+				goto todo;
+			}
+		}
+todo:
+		if (j == (val_cnt + 1)) {
+			x_val[j][0] = temp;
+			x_val[j][1] = 1;
+			val_cnt++;
+			rx_pr("new\n");
+		}
+		rx_pr("x_val=0x%x,cnt=%d,val_cnt=%d\n",
+		      x_val[j][0], x_val[j][1], val_cnt);
+
+		if (x_val[j][1] == 10) {
+			term_cal_val = (~((x_val[j][0]) << 1)) & 0x3ff;
+			for (; j < val_cnt; j++)
+				rx_pr("val=%x,cnt=%d\n",
+				      x_val[j][0], x_val[j][1]);
+			return;
+		}
+		j = 0;
+	}
+}
--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
@@ -1062,7 +1062,9 @@

 /* tl1 HIU PHY register */
 #define HHI_HDMIRX_PHY_MISC_CNTL0		(0xd7<<2)/*0x040*/
+#define MISCI_COMMON_RST				_BIT(10)
 #define HHI_HDMIRX_PHY_MISC_CNTL1		(0xd8<<2)/*0x041*/
+#define MISCI_MANUAL_MODE				_BIT(22)
 #define HHI_HDMIRX_PHY_MISC_CNTL2		(0xe0<<2)/*0x042*/
 #define HHI_HDMIRX_PHY_MISC_CNTL3		(0xe1<<2)/*0x043*/
 #define HHI_HDMIRX_PHY_DCHA_CNTL0		(0xe2<<2)/*0x045*/
@@ -1071,7 +1073,7 @@
 #define HHI_HDMIRX_PHY_DCHD_CNTL0		(0xe5<<2)/*0x048*/
 #define HHI_HDMIRX_PHY_DCHD_CNTL1		(0xe6<<2)/*0x049*/
 #define HHI_HDMIRX_PHY_DCHD_CNTL2		(0xe7<<2)/*0x04A*/
-/*#define HHI_HDMIRX_PHY_MISC_STAT		(0xee<<2)*//*0x044*/
+#define HHI_HDMIRX_PHY_MISC_STAT		(0xee << 2)//0x044
 #define HHI_HDMIRX_PHY_DCHD_STAT		(0xef<<2)/*0x04B*/

 #define TMDS_CLK_MIN			(24000UL)
@@ -1116,10 +1118,12 @@ extern int pll_rst_max;
 extern int cdr_lock_level;
 extern int top_intr_maskn_value;
 extern int hbr_force_8ch;
+extern bool term_cal_en;
 extern int clock_lock_th;
 extern int scdc_force_en;
 extern bool hdcp_hpd_ctrl_en;
 extern int eq_dbg_lvl;
+extern int phy_term_lel;

 extern void rx_get_best_eq_setting(void);
 extern void wr_reg_hhi(unsigned int offset, unsigned int val);
@@ -1307,6 +1311,9 @@ extern void rx_run_eq(void);
 extern bool rx_eq_done(void);
 extern bool is_tmds_valid(void);
 extern void hdmirx_top_irq_en(bool flag);
+void rx_phy_rt_cal(void);
+bool is_ft_trim_done(void);
+void aml_phy_get_trim_val(void);
 #endif


--- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
+++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
@@ -208,6 +208,7 @@ static int esd_phy_rst_cnt;
 static int esd_phy_rst_max;
 static int cec_dev_info;
 struct rx_s rx;
+static bool term_flag = 1;

 void hdmirx_init_params(void)
 {
@@ -2974,7 +2975,8 @@ int hdmirx_debug(const char *buf, int size)
 		rx.phy.err_sum = 0xffffff;
 	} else if (strncmp(tmpbuf, "audio", 5) == 0) {
 		hdmirx_audio_fifo_rst();
-	}
+	} else if (strncmp(tmpbuf, "eqcal", 5) == 0)
+		rx_phy_rt_cal();

 	return 0;
 }
@@ -3004,6 +3006,10 @@ void hdmirx_timer_handler(unsigned long arg)
 {
 	struct hdmirx_dev_s *devp = (struct hdmirx_dev_s *)arg;

+	if (term_flag && term_cal_en) {
+		rx_phy_rt_cal();
+		term_flag = 0;
+	}
 	rx_5v_monitor();
 	rx_check_repeat();
 	rx_dw_edid_monitor();