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drm/rockchip: vop2: enable vop urgency signal output for rk3576

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The urgency signal can improve the performance of VOP accessing DDR, since VP0
support 4K120hz output, it usually needs high performance and bandwidth, so it's
enabled at RK3576 VP0.

RK3576 VP0 has 8 lines post linebuffer, when full post line buffer is less 4,
the urgency signal will be set to 1, when full post line buffer is over 6, the
urgency signal will be set to 0.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If96a3bda6728b1faa36d03f0ae6f71b6a60558a3
This commit is contained in:
Sandy Huang
2024-04-01 10:42:50 +08:00
parent 84e4e6277c
commit 4796d94c3b
4 changed files with 51 additions and 0 deletions
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13
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -447,6 +447,11 @@ struct vop_intr {
struct vop_reg status;
};
struct vop_urgency {
u8 urgen_thl;
u8 urgen_thh;
};
struct vop_scl_extension {
struct vop_reg cbcr_vsd_mode;
struct vop_reg cbcr_vsu_mode;
@@ -979,6 +984,13 @@ struct vop2_video_port_regs {
struct vop_reg csc_offset1;
struct vop_reg csc_offset2;
/* axi urgency */
struct vop_reg axi0_port_urgency_en;
struct vop_reg axi1_port_urgency_en;
struct vop_reg post_urgency_en;
struct vop_reg post_urgency_thl;
struct vop_reg post_urgency_thh;
/* color bar */
struct vop_reg color_bar_en;
struct vop_reg color_bar_mode;
@@ -1182,6 +1194,7 @@ struct vop2_video_port_data {
const u8 win_dly;
const u8 pixel_rate;
const struct vop_intr *intr;
const struct vop_urgency *urgency;
const struct vop_hdr_table *hdr_table;
const struct vop2_video_port_regs *regs;
const struct vop3_ovl_regs *ovl_regs;

10
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -8996,6 +8996,16 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta
VOP_MODULE_SET(vop2, vp, almost_full_or_en, 1);
VOP_MODULE_SET(vop2, vp, line_flag_or_en, 1);
if (vop2->data->vp[vp->id].urgency) {
u8 urgen_thl = vop2->data->vp[vp->id].urgency->urgen_thl;
u8 urgen_thh = vop2->data->vp[vp->id].urgency->urgen_thh;
VOP_MODULE_SET(vop2, vp, axi0_port_urgency_en, 1);
VOP_MODULE_SET(vop2, vp, axi1_port_urgency_en, 1);
VOP_MODULE_SET(vop2, vp, post_urgency_en, 1);
VOP_MODULE_SET(vop2, vp, post_urgency_thl, urgen_thl);
VOP_MODULE_SET(vop2, vp, post_urgency_thh, urgen_thh);
}
if (vcstate->dsc_enable) {
if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
vop2_crtc_enable_dsc(crtc, old_cstate, 0);

26
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1577,6 +1577,11 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 20),
.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 28),
.axi0_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL0_IMD, 0x1, 24),
.axi1_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL1_IMD, 0x1, 24),
.post_urgency_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 8),
.post_urgency_thl = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0xf, 16),
.post_urgency_thh = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0xf, 20),
};
static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
@@ -1652,6 +1657,11 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 21),
.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 29),
.axi0_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL0_IMD, 0x1, 25),
.axi1_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL1_IMD, 0x1, 25),
.post_urgency_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 8),
.post_urgency_thl = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0xf, 16),
.post_urgency_thh = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0xf, 20),
};
static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
@@ -1727,6 +1737,11 @@ static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 22),
.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 30),
.axi0_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL0_IMD, 0x1, 26),
.axi1_port_urgency_en = VOP_REG(RK3576_SYS_AXI_HURRY_CTRL1_IMD, 0x1, 26),
.post_urgency_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 8),
.post_urgency_thl = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0xf, 16),
.post_urgency_thh = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0xf, 20),
};
static const struct vop3_ovl_regs rk3576_vop_vp0_ovl_regs = {
@@ -1735,6 +1750,16 @@ static const struct vop3_ovl_regs rk3576_vop_vp0_ovl_regs = {
.extra_mix_regs = &rk3576_vop_extra_mix_regs,
};
/*
* RK3576 VP0 has 8 lines post linebuffer, when full post line buffer is less 4,
* the urgency signal will be set to 1, when full post line buffer is over 6, the
* urgency signal will be set to 0.
*/
static const struct vop_urgency rk3576_vp0_urgency = {
.urgen_thl = 4,
.urgen_thh = 6,
};
static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
{
.id = 0,
@@ -1754,6 +1779,7 @@ static const struct vop2_video_port_data rk3576_vop_video_ports[] = {
.win_dly = 10,
.pixel_rate = 2,
.intr = &rk3568_vp0_intr,
.urgency = &rk3576_vp0_urgency,
.regs = &rk3576_vop_vp0_regs,
.ovl_regs = &rk3576_vop_vp0_ovl_regs,
},

2
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1050,6 +1050,8 @@
#define RK3568_VOP2_GLB_CFG_DONE_EN BIT(15)
#define RK3568_VERSION_INFO 0x004
#define RK3568_SYS_AUTO_GATING_CTRL 0x008
#define RK3576_SYS_AXI_HURRY_CTRL0_IMD 0x014
#define RK3576_SYS_AXI_HURRY_CTRL1_IMD 0x018
#define RK3576_SYS_MMU_CTRL_IMD 0x020
#define RK3568_SYS_AXI_LUT_CTRL 0x024
#define RK3568_DSP_IF_EN 0x028