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drm/rockchip: drv: remove unused rockchip_drm_get_dclk_by_width()

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We can get the vp max dclk rate from vop reg data, so the function
rockchip_drm_get_dclk_by_width() is unused now.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I88ccb372cdd75db008bcf5ec7913924d046240b8
This commit is contained in:
Sandy Huang
2024-03-29 16:00:55 +08:00
parent 742e1e510b
commit 84e4e6277c
2 changed files with 0 additions and 35 deletions
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34
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@@ -450,40 +450,6 @@ int rockchip_drm_add_modes_noedid(struct drm_connector *connector)
}
EXPORT_SYMBOL(rockchip_drm_add_modes_noedid);
static const struct rockchip_drm_width_dclk {
int width;
u32 dclk_khz;
} rockchip_drm_dclk[] = {
{1920, 148500},
{2048, 200000},
{2560, 280000},
{3840, 594000},
{4096, 594000},
{7680, 2376000},
};
u32 rockchip_drm_get_dclk_by_width(int width)
{
int i = 0;
u32 dclk_khz;
for (i = 0; i < ARRAY_SIZE(rockchip_drm_dclk); i++) {
if (width == rockchip_drm_dclk[i].width) {
dclk_khz = rockchip_drm_dclk[i].dclk_khz;
break;
}
}
if (i == ARRAY_SIZE(rockchip_drm_dclk)) {
DRM_ERROR("Can't not find %d width solution and use 148500 khz as max dclk\n", width);
dclk_khz = 148500;
}
return dclk_khz;
}
EXPORT_SYMBOL(rockchip_drm_get_dclk_by_width);
static const char * const color_encoding_name[] = {
[DRM_COLOR_YCBCR_BT601] = "BT.601",
[DRM_COLOR_YCBCR_BT709] = "BT.709",

1
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -599,7 +599,6 @@ int rockchip_drm_add_modes_noedid(struct drm_connector *connector);
void rockchip_drm_te_handle(struct drm_crtc *crtc);
void drm_mode_convert_to_split_mode(struct drm_display_mode *mode);
void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode);
u32 rockchip_drm_get_dclk_by_width(int width);
const char *rockchip_drm_get_color_encoding_name(enum drm_color_encoding encoding);
const char *rockchip_drm_get_color_range_name(enum drm_color_range range);
#if IS_REACHABLE(CONFIG_DRM_ROCKCHIP)