shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 20:07:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: vop2: Only do clk_round_rate check when dclk <= max_dclk

Browse Source 
The Current max vop_dclk if 600MHZ on all rockchip soc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I497fc14e89bcbaf4e6aa44fc36bc7fc93ac45aed
This commit is contained in:
Andy Yan
2021-11-19 19:15:14 +08:00
parent b3e060dc22
commit 47a1e8c992
1 changed files with 5 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -139,6 +139,8 @@
#define VOP2_SYS_AXI_BUS_NUM 2
#define VOP2_MAX_VP_OUTPUT_WIDTH 4096
/* KHZ */
#define VOP2_MAX_DCLK_RATE 600000
#define VOP2_COLOR_KEY_NONE (0 << 31)
#define VOP2_COLOR_KEY_MASK (1 << 31)
@@ -4869,9 +4871,9 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
adj_mode->crtc_clock *= 2;
adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
adj_mode->crtc_clock * 1000), 1000);
if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE)
adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
adj_mode->crtc_clock * 1000), 1000);
return true;
}