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ARM: dts: rockchip: add ai-cam-ddr3-v1 dts for ai cam ddr3 board
Signed-off-by: Huang zhibao <hzb@rock-chips.com> Change-Id: Ic9a504a3a8fe9465101a353640254259c952ae6b
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@@ -845,6 +845,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rv1109-evb-ddr3-v10.dtb \
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rv1109-evb-lp3-v10.dtb \
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rv1109-fpga.dtb \
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rv1126-ai-cam-ddr3-v1.dtb \
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rv1126-evb-ddr3-v10.dtb \
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rv1126-evb-ddr3-v10-tb.dtb \
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rv1126-evb-lp3-v10.dtb \
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65
arch/arm/boot/dts/rv1126-ai-cam-ddr3-v1.dts
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65
arch/arm/boot/dts/rv1126-ai-cam-ddr3-v1.dts
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@@ -0,0 +1,65 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
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*/
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/dts-v1/;
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#include "rv1126.dtsi"
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#include "rv11xx-ai-cam.dtsi"
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/ {
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model = "Rockchip RV1126 AI CAMERA DDR3L Board";
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compatible = "rockchip,rv1126-ai-cam-ddr3L-v1", "rockchip,rv1126";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait snd_aloop.index=7";
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};
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};
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&csi_dphy0 {
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status = "okay";
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ports {
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ucam_out0>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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gc4c33: gc4c33@29 {
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compatible = "galaxycore,gc4c33";
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reg = <0x29>;
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clocks = <&cru CLK_MIPICSI_OUT>;
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clock-names = "xvclk";
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power-domains = <&power RV1126_PD_VI>;
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pinctrl-names = "rockchip,camera_default";
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pinctrl-0 = <&mipi_csi_clk0>;
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pwren-gpios= <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <1>;
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rockchip,camera-module-facing = "front";
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rockchip,camera-module-name = "JSD3425-C1";
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rockchip,camera-module-lens-name = "JSD3425-C1";
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// NO_HDR:0 HDR_X2:5 HDR_X3:6
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rockchip,camera-hdr-mode = <0>;
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port {
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ucam_out0: endpoint {
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remote-endpoint = <&mipi_in_ucam0>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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