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arm64: dts: rockchip: Add RK3562 iotest board devicetree

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Jake Wu <jake.wu@rock-chips.com>
Change-Id: I1de47c3fc46e1e95c9ad77efa2b697edffdd5c6d
This commit is contained in:
Finley Xiao
2022-11-02 16:15:24 +08:00
committed by Tao Huang
parent 2df94e8259
commit 4aa12ffbf8
2 changed files with 83 additions and 0 deletions
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1
arch/arm64/boot/dts/rockchip/Makefile
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@@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb

82
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts Normal file
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@@ -0,0 +1,82 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3562.dtsi"
#include "rk3562-android.dtsi"
/ {
model = "Rockchip RK3562 IOTEST LP3 V10 Board";
compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562";
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
};
#include "rk3562-rk809.dtsi"
&combphy_pu {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbdrd_dwc3 {
status = "okay";
dr_mode = "otg";
extcon = <&u2phy>;
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
};