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Merge tag 'at91-dt-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt

Browse Source 
AT91 DT for 6.5

It contains:
- gpio-line-names addition for at91-tse850-3 board
- support for SMA connectors on lan966x-pcb8309 board
- use drive-open-drain as boolean property as this is how code handles
  it
- generic names for clock controller devices
- use of the new clock controller bindings for at91sam9n12 slow clock
  controller
- one blank line removal on sama5d2.dtsi

* tag 'at91-dt-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: at91: sama5d2: remove extra line
  ARM: dts: at91: Return to boolean properties
  ARM: dts: lan966x: Add support for SMA connectors
  ARM: dts: at91: use clock-controller name for sckc nodes
  ARM: dts: at91: at91sam9n12: witch sckc to new clock bindings
  ARM: dts: at91: use clock-controller name for PMC nodes
  ARM: dts: at91: tse850: add properties for gpio-line-names

Link: https://lore.kernel.org/r/20230530105945.11638-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2023-06-06 17:32:01 +02:00
parent 35ee6a4deb 4ceb0c70d0
commit 4d1010ff17
23 changed files with 105 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/at91-kizbox3-hs.dts
View File

@@ -225,7 +225,7 @@
pinctrl_pio_io_reset: gpio_io_reset {
pinmux = <PIN_PB30__GPIO>;
bias-disable;
drive-open-drain = <1>;
drive-open-drain;
output-low;
};
pinctrl_pio_input: gpio_input {

2
arch/arm/boot/dts/at91-kizbox3_common.dtsi
View File

@@ -211,7 +211,7 @@
pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA
<PIN_PD13__FLEXCOM4_IO1>; //CLK
bias-disable;
drive-open-drain = <1>;
drive-open-drain;
};
pinctrl_pwm0 {

60
arch/arm/boot/dts/at91-tse850-3.dts
View File

@@ -300,3 +300,63 @@
dmas = <0>, <0>; /* Do not use DMA for dbgu */
};
&pioA {
gpio-line-names =
/* 0 */ "SUP-A", "SUP-B", "SUP-C", "SIG<LEV",
/* 4 */ "", "/RFRST", "", "",
/* 8 */ "/ADD", "", "/LOOP1", "/LOOP2",
/* 12 */ "", "", "", "",
/* 16 */ "LED1GREEN", "LED1RED", "LED2GREEN", "LED2RED",
/* 20 */ "LED3GREEN", "LED3RED", "LED4GREEN", "LED4RED",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "SDA", "SCL";
};
&pioB {
gpio-line-names =
/* 0 */ "", "", "", "",
/* 4 */ "", "", "", "",
/* 8 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "SIG<LIN", "SIG>LIN",
/* 28 */ "RXD", "TXD", "BRX", "BTX";
};
&pioC {
gpio-line-names =
/* 0 */ "ETX0", "ETX1", "ERX0", "ERX1",
/* 4 */ "ETXEN", "ECRSDV", "ERXER", "EREFCK",
/* 8 */ "EMDC", "EMDIO", "", "",
/* 12 */ "", "", "", "/ILIM",
/* 16 */ "BCK", "LRCK", "DIN", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "VBUS";
};
&pioD {
gpio-line-names =
/* 0 */ "I1", "I2", "O1", "EXTVEN",
/* 4 */ "", "456KHZ", "VCTRL", "SYNCSEL",
/* 8 */ "STEREO", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", ">LIN", "LIN>", "",
/* 20 */ "VREFEN", "", "", "",
/* 24 */ "", "", "VINOK", "",
/* 28 */ "POEOK", "USBON", "POELOAD", "";
};
&pioE {
gpio-line-names =
/* 0 */ "", "", "", "",
/* 4 */ "", "", "", "",
/* 8 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "ALE", "CLE", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "/ETHINT";
};

2
arch/arm/boot/dts/at91rm9200.dtsi
View File

@@ -102,7 +102,7 @@
reg = <0xffffff00 0x100>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91rm9200-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

2
arch/arm/boot/dts/at91sam9260.dtsi
View File

@@ -115,7 +115,7 @@
reg = <0xffffee00 0x200>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

2
arch/arm/boot/dts/at91sam9261.dtsi
View File

@@ -599,7 +599,7 @@
};
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9261-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

2
arch/arm/boot/dts/at91sam9263.dtsi
View File

@@ -101,7 +101,7 @@
atmel,external-irqs = <30 31>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9263-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;

2
arch/arm/boot/dts/at91sam9g20.dtsi
View File

@@ -41,7 +41,7 @@
atmel,adc-startup-time = <40>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon";
};
};

2
arch/arm/boot/dts/at91sam9g25.dtsi
View File

@@ -26,7 +26,7 @@
>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};

2
arch/arm/boot/dts/at91sam9g35.dtsi
View File

@@ -25,7 +25,7 @@
>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};

4
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@@ -129,7 +129,7 @@
reg = <0xffffea00 0x200>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g45-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -923,7 +923,7 @@
status = "disabled";
};
clk32k: sckc@fffffd50 {
clk32k: clock-controller@fffffd50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffd50 0x4>;
clocks = <&slow_xtal>;

25
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@@ -118,7 +118,7 @@
reg = <0xffffea00 0x200>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9n12-pmc", "syscon";
reg = <0xfffffc00 0x200>;
#clock-cells = <2>;
@@ -146,28 +146,11 @@
clocks = <&clk32k>;
};
sckc@fffffe50 {
clk32k: clock-controller@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
slow_osc: slow_osc {
compatible = "atmel,at91sam9x5-clk-slow-osc";
#clock-cells = <0>;
clocks = <&slow_xtal>;
};
slow_rc_osc: slow_rc_osc {
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
clk32k: slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc>, <&slow_osc>;
};
clocks = <&slow_xtal>;
#clock-cells = <0>;
};
mmc0: mmc@f0008000 {

4
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@@ -763,7 +763,7 @@
};
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9rl-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -799,7 +799,7 @@
status = "disabled";
};
clk32k: sckc@fffffd50 {
clk32k: clock-controller@fffffd50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffd50 0x4>;
clocks = <&slow_xtal>;

2
arch/arm/boot/dts/at91sam9x25.dtsi
View File

@@ -27,7 +27,7 @@
>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};

2
arch/arm/boot/dts/at91sam9x35.dtsi
View File

@@ -26,7 +26,7 @@
>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};

4
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@@ -126,7 +126,7 @@
reg = <0xffffea00 0x200>;
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -154,7 +154,7 @@
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
clk32k: sckc@fffffe50 {
clk32k: clock-controller@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;

14
arch/arm/boot/dts/lan966x-pcb8309.dts
View File

@@ -144,6 +144,18 @@
function = "fc4_b";
};
pps_out_pins: pps-out-pins {
/* 1pps output */
pins = "GPIO_38";
function = "ptpsync_3";
};
ptp_ext_pins: ptp-ext-pins {
/* 1pps input */
pins = "GPIO_39";
function = "ptpsync_4";
};
sgpio_a_pins: sgpio-a-pins {
/* SCK, D0, D1, LD */
pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
@@ -212,5 +224,7 @@
};
&switch {
pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
pinctrl-names = "default";
status = "okay";
};

4
arch/arm/boot/dts/sam9x60.dtsi
View File

@@ -1282,7 +1282,7 @@
};
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "microchip,sam9x60-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -1322,7 +1322,7 @@
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
clk32k: sckc@fffffe50 {
clk32k: clock-controller@fffffe50 {
compatible = "microchip,sam9x60-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;

5
arch/arm/boot/dts/sama5d2.dtsi
View File

@@ -284,7 +284,7 @@
clock-names = "dma_clk";
};
pmc: pmc@f0014000 {
pmc: clock-controller@f0014000 {
compatible = "atmel,sama5d2-pmc", "syscon";
reg = <0xf0014000 0x160>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -704,10 +704,9 @@
status = "disabled";
};
clk32k: sckc@f8048050 {
clk32k: clock-controller@f8048050 {
compatible = "atmel,sama5d4-sckc";
reg = <0xf8048050 0x4>;
clocks = <&slow_xtal>;
#clock-cells = <0>;
};

4
arch/arm/boot/dts/sama5d3.dtsi
View File

@@ -1001,7 +1001,7 @@
};
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
compatible = "atmel,sama5d3-pmc", "syscon";
reg = <0xfffffc00 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -1040,7 +1040,7 @@
status = "disabled";
};
clk32k: sckc@fffffe50 {
clk32k: clock-controller@fffffe50 {
compatible = "atmel,sama5d3-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;

2
arch/arm/boot/dts/sama5d3_emac.dtsi
View File

@@ -30,7 +30,7 @@
};
};
pmc: pmc@fffffc00 {
pmc: clock-controller@fffffc00 {
};
macb1: ethernet@f802c000 {

4
arch/arm/boot/dts/sama5d4.dtsi
View File

@@ -250,7 +250,7 @@
clock-names = "dma_clk";
};
pmc: pmc@f0018000 {
pmc: clock-controller@f0018000 {
compatible = "atmel,sama5d4-pmc", "syscon";
reg = <0xf0018000 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -761,7 +761,7 @@
status = "disabled";
};
clk32k: sckc@fc068650 {
clk32k: clock-controller@fc068650 {
compatible = "atmel,sama5d4-sckc";
reg = <0xfc068650 0x4>;
#clock-cells = <0>;

2
arch/arm/boot/dts/sama7g5.dtsi
View File

@@ -241,7 +241,7 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
};
pmc: pmc@e0018000 {
pmc: clock-controller@e0018000 {
compatible = "microchip,sama7g5-pmc", "syscon";
reg = <0xe0018000 0x200>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;