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clk: rockchip: rv1126b: Add ROCKCHIP_PLL_ALLOW_POWER_DOWN for aupll

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: If7d656534db6ec000ceabe4a6214ada01e1dd102
This commit is contained in:
Finley Xiao
2025-04-09 16:47:57 +08:00
committed by Tao Huang
parent 9391198085
commit 4d3dbab67b
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/rockchip/clk-rv1126b.c
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@@ -150,7 +150,8 @@ static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = {
RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates),
[aupll] = PLL(pll_rk3328, PLL_AUPLL, "aupll", mux_pll_p,
0, RV1126B_PLL_CON(0),
RV1126B_MODE_CON, 0, 10, 0, rv1126b_pll_rates),
RV1126B_MODE_CON, 0, 10,
ROCKCHIP_PLL_ALLOW_POWER_DOWN, rv1126b_pll_rates),
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0),
RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates),