shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 11:26:02 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: rv1106: optimize clk registration

Browse Source 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I498621bed6b6a6049b092d1aa3f2c4fd93176079
This commit is contained in:
Elaine Zhang
2022-03-22 16:31:26 +08:00
committed by Tao Huang
parent 9e7c1cf22b
commit 4d5e7c1061
1 changed files with 22 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
drivers/clk/rockchip/clk-rv1106.c
View File

@@ -275,28 +275,6 @@ static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_cpu_root", 0,
RV1106_CORECLKGATE_CON(1), 8, GFLAGS),
/* PD_DDR */
COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
RV1106_DDRCLKSEL_CON(0), 0, 2, MFLAGS,
RV1106_DDRCLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_DDR_ROOT, "aclk_ddr_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
RV1106_DDRCLKSEL_CON(0), 8, 2, MFLAGS,
RV1106_DDRCLKGATE_CON(0), 12, GFLAGS),
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
RV1106_DDRCLKGATE_CON(1), 3, GFLAGS),
GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
RV1106_DDRCLKGATE_CON(1), 2, GFLAGS),
GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
RV1106_DDRCLKGATE_CON(0), 7, GFLAGS),
GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
RV1106_DDRCLKGATE_CON(0), 8, GFLAGS),
GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
RV1106_DDRCLKGATE_CON(0), 5, GFLAGS),
GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
RV1106_DDRCLKGATE_CON(0), 11, GFLAGS),
GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
RV1106_DDRCLKGATE_CON(0), 13, GFLAGS),
/* PD _TOP */
COMPOSITE(CLK_50M_SRC, "clk_50m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
RV1106_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
@@ -447,6 +425,28 @@ static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
RV1106_CLKSEL_CON(23), 8, 1, MFLAGS, 3, 5, DFLAGS,
RV1106_CLKGATE_CON(2), 6, GFLAGS),
/* PD_DDR */
COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
RV1106_DDRCLKSEL_CON(0), 0, 2, MFLAGS,
RV1106_DDRCLKGATE_CON(0), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_DDR_ROOT, "aclk_ddr_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
RV1106_DDRCLKSEL_CON(0), 8, 2, MFLAGS,
RV1106_DDRCLKGATE_CON(0), 12, GFLAGS),
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
RV1106_DDRCLKGATE_CON(1), 3, GFLAGS),
GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
RV1106_DDRCLKGATE_CON(1), 2, GFLAGS),
GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
RV1106_DDRCLKGATE_CON(0), 7, GFLAGS),
GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
RV1106_DDRCLKGATE_CON(0), 8, GFLAGS),
GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
RV1106_DDRCLKGATE_CON(0), 5, GFLAGS),
GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
RV1106_DDRCLKGATE_CON(0), 11, GFLAGS),
GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
RV1106_DDRCLKGATE_CON(0), 13, GFLAGS),
/* PD_NPU */
COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
RV1106_NPUCLKSEL_CON(0), 0, 2, MFLAGS,