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cpufreq: rockchip: Add support to set intermediate rate
When increase voltage the cpu frequency is increased at the same time, but the read margin has not been reduced. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Change-Id: I97097a5114abad193b7a29aeada390d0323b10ba
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@@ -36,6 +36,11 @@
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#include "cpufreq-dt.h"
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#include "rockchip-cpufreq.h"
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#define CPUFREQ_INTERNAL_VERSION 0x80
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#define CPUFREQ_LENGTH_MARGIN 0x1
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#define CPUFREQ_INTERMEDIATE_RATE (CPUFREQ_INTERNAL_VERSION | \
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CPUFREQ_LENGTH_MARGIN)
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struct cluster_info {
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struct list_head list_head;
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struct monitor_dev_info *mdev_info;
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@@ -350,6 +355,16 @@ static int rockchip_cpufreq_set_read_margin(struct device *dev,
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return 0;
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}
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static int
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rockchip_cpufreq_set_intermediate_rate(struct rockchip_opp_info *opp_info,
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struct clk *clk, unsigned long new_freq)
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{
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if (opp_info->data && opp_info->data->set_read_margin)
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return clk_set_rate(clk, new_freq | CPUFREQ_INTERMEDIATE_RATE);
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return 0;
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}
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static int cpu_opp_helper(struct dev_pm_set_opp_data *data)
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{
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struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];
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@@ -373,6 +388,13 @@ static int cpu_opp_helper(struct dev_pm_set_opp_data *data)
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/* Scaling up? Scale voltage before frequency */
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if (new_freq >= old_freq) {
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ret = rockchip_cpufreq_set_intermediate_rate(opp_info, clk,
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new_freq);
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if (ret) {
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dev_err(dev, "%s: failed to set clk rate: %lu\n",
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__func__, new_freq);
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return -EINVAL;
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}
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ret = rockchip_cpufreq_set_volt(dev, mem_reg, new_supply_mem,
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"mem");
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if (ret)
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