shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

phy/rockchip: samsung-hdptx: Disable TX jitter EQ for power reduction

Browse Source 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia5a0901182deb47b1a8599922efbcf60101ce15c
This commit is contained in:
Wyon Bi
2022-04-14 03:26:29 +00:00
committed by Tao Huang
parent b6b135b2f6
commit 50e757f7cb
1 changed files with 0 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
View File

@@ -491,31 +491,15 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
{
const struct tx_drv_ctrl *ctrl;
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),
LN_ANA_TX_JEQ_EN,
FIELD_PREP(LN_ANA_TX_JEQ_EN, 0x1));
switch (dp->link_rate) {
case 1620:
ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28),
LN_TX_JEQ_EVEN_CTRL_RBR,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR, 0x7));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30),
LN_TX_JEQ_ODD_CTRL_RBR,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR, 0x7));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_RBR,
FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1));
break;
case 2700:
ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
LN_TX_JEQ_EVEN_CTRL_HBR,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, 0x7));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
LN_TX_JEQ_ODD_CTRL_HBR,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, 0x7));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_HBR,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));
@@ -523,12 +507,6 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
case 5400:
default:
ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c),
LN_TX_JEQ_EVEN_CTRL_HBR2,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, 0x7));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34),
LN_TX_JEQ_ODD_CTRL_HBR2,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, 0x7));
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_HBR2,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));