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mmc/sdhc: Fix clk_div for maximum clock

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Change-Id: I5dabc4071c2f1d2d4f4ea550097b990757c74e99
Signed-off-by: Kevin Kim <chkim@hardkernel.com>
(cherry picked from commit 18dc68ff78151320c4a6133f5731448d2ac4f500)
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
This commit is contained in:
ckkim
2014-10-30 18:29:26 +09:00
committed by Dongjin Kim
parent 53b0e22817
commit 5134a48cbe
1 changed files with 2 additions and 0 deletions
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2
drivers/amlogic/mmc/aml_sdhc_m8.c
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@@ -1988,8 +1988,10 @@ static void aml_sdhc_set_clk_rate(struct mmc_host *mmc, unsigned int clk_ios)
/*0: dont set it, 1:div2, 2:div3, 3:div4...*/
clk_div = clk_rate / clk_ios - !(clk_rate%clk_ios);
#if !defined(CONFIG_MACH_MESON8B_ODROIDC)
if (!(clk_div & 0x01)) // if even number, turn it to an odd one
clk_div++;
#endif
aml_sdhc_clk_switch(pdata, clk_div, clk_src_sel);
pdata->clkc = readl(host->base+SDHC_CLKC);