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phy: rockchip: mipi-dcphy: fix PLL VCO restrictions

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Frequency of VCO's output: 2600MHz ≤ Fvco ≤ 6600MHz

Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Iace886293b9d30d0cedcae4ad56582109c5ee716
This commit is contained in:
Guochun Huang
2021-12-08 19:32:37 +08:00
committed by Tao Huang
parent 3278e8cadf
commit 52439761bf
1 changed files with 5 additions and 1 deletions
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6
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
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@@ -1466,7 +1466,11 @@ samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung,
/* 0 ≤ S[2:0] ≤ 6 */
for (_scaler = 0; _scaler < 7; _scaler++) {
fvco = fout << _scaler;
if (fvco > max_fout)
/*
* 2600MHz ≤ FVCO ≤ 6600MHz
*/
if (fvco < 2600 || fvco > 6600)
continue;
/* 6MHz ≤ Fref(Fin / p) ≤ 30MHz */