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drm/rockchip: vop2: get hdmi phy clk rate rate before set

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hdmi phy clk rate may change by hdmi controller, while clk framework
don't know that, whick may set wrong dclk rate when use hdmi phy pll
as dclk parent. So It necessary to update the hdmi phy pll clk rate
before set a new clk rate.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I4ca6d5e34f0459ecbcfa894e9a136d05408160a0
This commit is contained in:
Zhang Yubing
2022-03-29 09:20:01 +08:00
committed by Tao Huang
parent 6a2cb4bacc
commit 530d2fa793
1 changed files with 5 additions and 0 deletions
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5
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -3608,6 +3608,11 @@ static int vop2_clk_set_parent_extend(struct vop2_video_port *vp,
hdmi0_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
hdmi1_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
if (hdmi0_phy_pll)
clk_get_rate(hdmi0_phy_pll->clk);
if (hdmi1_phy_pll)
clk_get_rate(hdmi1_phy_pll->clk);
if ((!hdmi0_phy_pll && !hdmi1_phy_pll) ||
((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) && !hdmi0_phy_pll) ||
((vcstate->output_if & VOP_OUTPUT_IF_HDMI1) && !hdmi1_phy_pll))