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ARM: dts: rockchip: rv1126: Add leakage info for cpu, npu and vepu

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia0f0b61f77d22708064058960d38b240988d9bc3
This commit is contained in:
Finley Xiao
2020-10-13 21:11:05 +08:00
committed by Tao Huang
parent 3aa3abee3e
commit 57dfaaf4e6
1 changed files with 13 additions and 0 deletions
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13
arch/arm/boot/dts/rv1126.dtsi
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@@ -109,6 +109,10 @@
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "leakage";
rockchip,reboot-freq = <816000>;
rockchip,temp-freq-table = <
@@ -1358,6 +1362,9 @@
npu_leakage: npu-leakage@19 {
reg = <0x19 0x1>;
};
venc_leakage: venc-leakage@1a {
reg = <0x1a 0x1>;
};
cpu_tsadc_trim_l: cpu-tsadc-trim-l@23 {
reg = <0x23 0x1>;
};
@@ -2145,6 +2152,9 @@
rkvenc_opp_table: rkvenc-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&venc_leakage>;
nvmem-cell-names = "leakage";
rockchip,temp-freq-table = <
80000 500000
100000 396000
@@ -2338,6 +2348,9 @@
npu_opp_table: npu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&npu_leakage>;
nvmem-cell-names = "leakage";
clocks = <&pmucru PLL_GPLL>;
rockchip,bin-scaling-sel = <
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