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clk: rockchip: px30: mark dpll as critical

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Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ie72aecf05bcc6f3081f7f837c6ead4a680f9e2f3
This commit is contained in:
Elaine Zhang
2023-12-14 17:41:54 +08:00
committed by Tao Huang
parent 327743d8b6
commit 5b781b56ee
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-px30.c
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@@ -191,7 +191,7 @@ static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
CLK_IS_CRITICAL, PX30_PLL_CON(0),
PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0, PX30_PLL_CON(8),
CLK_IS_CRITICAL, PX30_PLL_CON(8),
PX30_MODE_CON, 4, 1, 0, NULL),
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0, PX30_PLL_CON(16),