shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: clock: add efuse clock for g12a

Browse Source 
PD#168568: clock: add efuse clock

Change-Id: I4ef07515db93fd8bf7108bfbe622d0ce261ed2d6
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
This commit is contained in:
Shunzhou Jiang
2018-07-06 10:13:26 +08:00
committed by Yixun Lan
parent 14dc230878
commit 5d4de95a06
3 changed files with 9 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/amlogic/clk/g12a/g12a.c
View File

@@ -654,6 +654,7 @@ static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
static MESON_GATE(g12a_efuse, HHI_GCLK_SP_MPEG, 1);
/* Array of all clocks provided by this provider */
@@ -742,6 +743,7 @@ static struct clk_hw *g12a_clk_hws[] = {
[CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
[CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
[CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
[CLKID_EFUSE] = &g12a_efuse.hw,
[CLKID_CPU_FCLK_P] = &g12a_cpu_fclk_p.hw,
[CLKID_CPU_CLK] = &g12a_cpu_clk.mux.hw,
@@ -833,6 +835,7 @@ static struct clk_gate *g12a_clk_gates[] = {
&g12a_vclk2_venclmmc,
&g12a_vclk2_vencl,
&g12a_vclk2_other1,
&g12a_efuse,
&g12a_24m,
&g12a_12m_gate,
};

1
drivers/amlogic/clk/g12a/g12a.h
View File

@@ -44,6 +44,7 @@
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
#define HHI_GCLK_SP_MPEG 0x154 /* 0x55 offset in data sheet */
#define HHI_APICALGDC_CNTL 0x168 /* 0x5a offset in data sheet */

6
include/dt-bindings/clock/amlogic,g12a-clkc.h
View File

@@ -132,7 +132,11 @@
#define CLKID_VCLK2_VENCL (GATE_BASE3 + 17)
#define CLKID_VCLK2_OTHER1 (GATE_BASE3 + 18)
#define GATE_AO_BASE (GATE_BASE3 + 19)
/*HHI_GCLK_SP_MPEG: 0x55*/
#define GATE_BASE4 (GATE_BASE3 + 19)
#define CLKID_EFUSE (GATE_BASE4 + 0)
#define GATE_AO_BASE (GATE_BASE4 + 1)
#define CLKID_AO_MEDIA_CPU (GATE_AO_BASE + 0)
#define CLKID_AO_AHB_SRAM (GATE_AO_BASE + 1)
#define CLKID_AO_AHB_BUS (GATE_AO_BASE + 2)