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clk: rockchip: rk3588: Fix pll rate table for 216MHz and 96MHz

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I06b086dab6f1a6663804f032ad4a3ea905d4bf23
This commit is contained in:
Finley Xiao
2022-01-08 18:14:40 +08:00
committed by Tao Huang
parent 0f6af0bdd7
commit 5db5a4cf85
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3588.c
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@@ -88,8 +88,8 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
RK3588_PLL_RATE(216000000, 2, 216, 3, 0),
RK3588_PLL_RATE(96000000, 2, 216, 3, 0),
RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
{ /* sentinel */ },
};