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clk: fixed gp0_pll spell error

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PD#151164: fixed gp0_pll spell error

Change-Id: I06b0c03492ad97260a1a12ca9f3882a8ec579388
Signed-off-by: Jiyu Yang <Jiyu.Yang@amlogic.com>
This commit is contained in:
Jiyu Yang
2017-10-28 16:04:54 +08:00
committed by Jiyu Yang
parent 3347f3d676
commit 5e1410d56b
4 changed files with 9 additions and 9 deletions
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6
arch/arm64/boot/dts/amlogic/mesongxbb-gpu-mali450.dtsi
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@@ -27,7 +27,7 @@
0x0 0x0 0x0 0x1 0x2 0x0>;
pmu_switch_delay = <0xffff> ;
num_of_pp = <3> ;
def_clk = <2> ;
def_clk = <4> ;
sc_mpp = <3>;/* number of pp used most of time.*/
tbl = <&clk125_cfg
&clk285_cfg
@@ -36,8 +36,8 @@
&clk666_cfg
&clk800_cfg>;
clocks = <&clkc CLKID_GPU_MUX>;
clock-names = "gpu_mux";
clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>;
clock-names = "gpu_mux","gp0_pll";
/*control_interval x keep_count == 900 - 1000ms */
control_interval = <200>;

4
arch/arm64/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi
View File

@@ -40,8 +40,8 @@
&dvfs666_cfg
&dvfs750_cfg>;
clocks = <&clkc CLKID_GPU_MUX>;
clock-names = "gpu_mux";
clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>;
clock-names = "gpu_mux","gp0_pll";
dvfs125_cfg:clk125_cfg {
clk_freq = <125000000>;

4
arch/arm64/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi
View File

@@ -40,8 +40,8 @@
&dvfs666_cfg
&dvfs666_cfg>;
clocks = <&clkc CLKID_GPU_MUX>;
clock-names = "gpu_mux";
clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>;
clock-names = "gpu_mux","gp0_pll";
dvfs125_cfg:clk125_cfg {
clk_freq = <125000000>;

4
drivers/amlogic/clk/gxl/clk_gpu.c
View File

@@ -26,8 +26,8 @@
#include "../clkc.h"
#include "gxl.h"
const char *gpu_parent_names[] = { "xtal", "gp0", "mpll2", "mpll1", "fclk_div7",
"fclk_div4", "fclk_div3", "fclk_div5"};
const char *gpu_parent_names[] = { "xtal", "gp0_pll", "mpll2", "mpll1",
"fclk_div7", "fclk_div4", "fclk_div3", "fclk_div5"};
static struct clk_mux gpu_p0_mux = {
.reg = (void *)HHI_MALI_CLK_CNTL,