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drm/rockchip: dsi: fix phy pll programming order

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The order of the write registers is as follows:
0x17->0x18(lsb)->0x19->0x18(msb)->0x19

Change-Id: I3164a46ed49be611db5bd62d2ae7810613bdbfe0
Signed-off-by: Jerry Xu <xbl@rock-chips.com>
This commit is contained in:
Jerry Xu
2017-09-28 10:49:41 +08:00
committed by Huang, Tao
parent 0f4abff0dd
commit 5fbe472645
1 changed files with 1 additions and 0 deletions
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drivers/gpu/drm/rockchip/dw-mipi-dsi.c
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@@ -527,6 +527,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div));
val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN;
dw_mipi_dsi_phy_write(dsi, 0x18, val);
dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN;
dw_mipi_dsi_phy_write(dsi, 0x18, val);
dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);