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UPSTREAM: spi: rockchip: always use SPI mode

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The hardware supports 3 different variants of SPI
and there were some code around it, but nothing
to actually set it to anything but "Motorola SPI".
Just drop that code and always use that mode.

Change-Id: I53d65943b80abea21f3bf35b440d56dc8a1190de
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 2410d6a3c3)
This commit is contained in:
Emil Renner Berthing
2018-10-31 11:57:00 +01:00
committed by Tao Huang
parent 116a5ae782
commit 6097c07d90
1 changed files with 4 additions and 13 deletions
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17
drivers/spi/spi-rockchip.c
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@@ -163,12 +163,6 @@
#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
enum rockchip_ssi_type {
SSI_MOTO_SPI = 0,
SSI_TI_SSP,
SSI_NS_MICROWIRE,
};
struct rockchip_spi_dma_data {
struct dma_chan *ch;
dma_addr_t addr;
@@ -186,8 +180,6 @@ struct rockchip_spi {
u32 fifo_len;
/* max bus freq supported */
u32 max_freq;
/* supported slave numbers */
enum rockchip_ssi_type type;
u16 mode;
u8 tmode;
@@ -547,14 +539,14 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
u32 dmacr = 0;
int rsd = 0;
u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
| (CR0_SSD_ONE << CR0_SSD_OFFSET)
| (CR0_EM_BIG << CR0_EM_OFFSET);
u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
| CR0_BHT_8BIT << CR0_BHT_OFFSET
| CR0_SSD_ONE << CR0_SSD_OFFSET
| CR0_EM_BIG << CR0_EM_OFFSET;
cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
cr0 |= (rs->tmode << CR0_XFM_OFFSET);
cr0 |= (rs->type << CR0_FRF_OFFSET);
if (rs->use_dma) {
if (rs->tx)
@@ -745,7 +737,6 @@ static int rockchip_spi_probe(struct platform_device *pdev)
spi_enable_chip(rs, false);
rs->type = SSI_MOTO_SPI;
rs->master = master;
rs->dev = &pdev->dev;
rs->max_freq = clk_get_rate(rs->spiclk);