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osd: enable osd rdma and afbc function

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PD#156734: osd: enable rdma and afbc function

Change-Id: I62b7a3bd84b758455deb2f614c763a145f751f63
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2018-02-08 00:05:07 +08:00
committed by Yixun Lan
parent 736aa794ce
commit 634ac8305c
9 changed files with 1086 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/amlogic/g12a_skt.dts
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@@ -1002,8 +1002,8 @@
/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
display_size_default = <1920 1080 1920 2160 32>;
/*1920*1080*4*3 = 0x17BB000*/
pxp_mode = <1>; /** 0:normal mode 1:pxp mode */
mem_alloc = <1>;
pxp_mode = <0>; /** 0:normal mode 1:pxp mode */
mem_alloc = <0>;
logo_addr = "0x3f800000";
};

2
drivers/amlogic/media/osd/osd.h
View File

@@ -551,7 +551,7 @@ struct hw_para_s {
u32 vinfo_width;
u32 vinfo_height;
u32 fb_drvier_probe;
u32 afbc_restart_in_vsync;
u32 afbc_start_in_vsync;
u32 afbc_force_reset;
u32 afbc_status_err_reset;
u32 afbc_use_latch;

1010
drivers/amlogic/media/osd/osd_backup.c
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File diff suppressed because it is too large Load Diff

4
drivers/amlogic/media/osd/osd_backup.h
View File

@@ -26,7 +26,7 @@
#define OSD_VALUE_COUNT (VIU_OSD1_CTRL_STAT2 - VIU_OSD1_CTRL_STAT + 1)
#define OSD_AFBC_VALUE_COUNT (OSD1_AFBCD_PIXEL_VSCOPE - OSD1_AFBCD_ENABLE + 1)
#define MALI_AFBC_VALUE_COUNT \
(VPU_MAFBC_PREFETCH_CFG_S2 - VPU_MAFBC_COMMAND + 1)
(VPU_MAFBC_PREFETCH_CFG_S2 - VPU_MAFBC_IRQ_MASK + 1)
extern const u16 osd_reg_backup[OSD_REG_BACKUP_COUNT];
extern const u16 osd_afbc_reg_backup[OSD_AFBC_REG_BACKUP_COUNT];
@@ -39,6 +39,8 @@ enum hw_reset_flag_e {
HW_RESET_NONE = 0,
HW_RESET_AFBCD_REGS = 0x80000000,
HW_RESET_OSD1_REGS = 0x00000001,
HW_RESET_OSD2_REGS = 0x00000002,
HW_RESET_OSD3_REGS = 0x00000004,
HW_RESET_AFBCD_HARDWARE = 0x80000000,
HW_RESET_MALI_AFBCD_REGS = 0x200000,
};

2
drivers/amlogic/media/osd/osd_drm.c
View File

@@ -732,9 +732,9 @@ void osd_drm_vsync_isr_handler(void)
/* go through update list */
walk_through_update_list();
osd_update_3d_mode();
osd_mali_afbc_start();
osd_update_vsync_hit();
osd_hw_reset();
osd_mali_afbc_restart();
} else {
if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG)
osd_rdma_interrupt_done_clear();

121
drivers/amlogic/media/osd/osd_hw.c
View File

@@ -1129,7 +1129,7 @@ void osd_hw_reset(void)
int i;
u32 addr;
u32 value;
u32 base = VPU_MAFBC_COMMAND;
u32 base = VPU_MAFBC_IRQ_MASK;
for (i = 0; i < MALI_AFBC_REG_BACKUP_COUNT; i++) {
addr = mali_afbc_reg_backup[i];
@@ -1137,8 +1137,8 @@ void osd_hw_reset(void)
VSYNCOSD_IRQ_WR_MPEG_REG(
addr, value);
}
VSYNCOSD_IRQ_WR_MPEG_REG(VPU_MAFBC_COMMAND, 1);
}
} else
osd_rdma_reset_and_flush(reset_bit);
spin_unlock_irqrestore(&osd_lock, lock_flags);
@@ -1182,9 +1182,9 @@ static irqreturn_t vsync_isr(int irq, void *dev_id)
/* go through update list */
walk_through_update_list();
osd_update_3d_mode();
osd_mali_afbc_start();
osd_update_vsync_hit();
osd_hw_reset();
osd_mali_afbc_restart();
} else
osd_rdma_interrupt_done_clear();
@@ -2361,7 +2361,7 @@ void osd_set_premult(u32 index, u32 premult)
void osd_get_afbc_debug(u32 *val1, u32 *val2, u32 *val3, u32 *val4)
{
*val1 = osd_hw.afbc_restart_in_vsync;
*val1 = osd_hw.afbc_start_in_vsync;
*val2 = osd_hw.afbc_force_reset;
*val3 = osd_hw.afbc_status_err_reset;
*val4 = osd_hw.afbc_use_latch;
@@ -2369,7 +2369,7 @@ void osd_get_afbc_debug(u32 *val1, u32 *val2, u32 *val3, u32 *val4)
void osd_set_afbc_debug(u32 val1, u32 val2, u32 val3, u32 val4)
{
osd_hw.afbc_restart_in_vsync = val1;
osd_hw.afbc_start_in_vsync = val1;
osd_hw.afbc_force_reset = val2;
osd_hw.afbc_status_err_reset = val3;
osd_hw.afbc_use_latch = val4;
@@ -2420,31 +2420,31 @@ const struct color_bit_define_s extern_color_format_array[] = {
{
COLOR_INDEX_32_ABGR, 2, 5,
0, 8, 0, 8, 8, 0, 16, 8, 0, 24, 8, 0,
0, 4
0, 32
},
/*32 bit color RGBX */
{
COLOR_INDEX_32_XBGR, 2, 5,
0, 8, 0, 8, 8, 0, 16, 8, 0, 24, 0, 0,
0, 4
0, 32
},
/*24 bit color RGB */
{
COLOR_INDEX_24_RGB, 5, 7,
16, 8, 0, 8, 8, 0, 0, 8, 0, 0, 0, 0,
0, 3
0, 24
},
/*16 bit color BGR */
{
COLOR_INDEX_16_565, 4, 4,
11, 5, 0, 5, 6, 0, 0, 5, 0, 0, 0, 0,
0, 2
0, 16
},
/*32 bit color BGRA */
{
COLOR_INDEX_32_ARGB, 1, 5,
16, 8, 0, 8, 8, 0, 0, 8, 0, 24, 8, 0,
0, 4
0, 32
},
};
@@ -2472,7 +2472,7 @@ static bool osd_ge2d_compose_pan_display(struct osd_fence_map_s *fence_map)
canvas_config(osd_hw.fb_gem[index].canvas_idx,
fence_map->ext_addr,
CANVAS_ALIGNED(fence_map->width *
osd_hw.color_info[index]->bpp),
(osd_hw.color_info[index]->bpp >> 3)),
fence_map->height,
CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
@@ -2856,6 +2856,8 @@ static void osd_pan_display_fence(struct osd_fence_map_s *fence_map)
osd_hw.reg[OSD_ENABLE]
.update_func(index);
}
if (osd_hw.hw_rdma_en)
osd_mali_afbc_start();
spin_unlock_irqrestore(&osd_lock, lock_flags);
osd_wait_vsync_hw();
} else if (xoffset != osd_hw.pandata[index].x_start
@@ -2964,6 +2966,8 @@ static void osd_pan_display_fence(struct osd_fence_map_s *fence_map)
osd_hw.reg[OSD_ENABLE]
.update_func(index);
}
if (osd_hw.hw_rdma_en)
osd_mali_afbc_start();
spin_unlock_irqrestore(&osd_lock, lock_flags);
osd_wait_vsync_hw();
} else if ((osd_enable != osd_hw.enable[index])
@@ -2973,6 +2977,8 @@ static void osd_pan_display_fence(struct osd_fence_map_s *fence_map)
if (!osd_hw.osd_display_debug)
osd_hw.reg[OSD_ENABLE]
.update_func(index);
if (osd_hw.hw_rdma_en)
osd_mali_afbc_start();
spin_unlock_irqrestore(&osd_lock, lock_flags);
osd_wait_vsync_hw();
}
@@ -3830,11 +3836,11 @@ static void osd_update_color_mode(u32 index)
/* 0 Block split mode off.
* 1 Block split mode on.
*/
u32 yuv_transform = 0;
u32 yuv_transform = 1;
/* 0 Internal YUV transform off.
* 1 Internal YUV transform on.
*/
u32 afbc_color_reorder = 0x4321;
u32 afbc_color_reorder = 0x1234;
/* 0x4321 = ABGR
* 0x1234 = RGBA
*/
@@ -3969,10 +3975,12 @@ static void osd_update_enable(u32 index)
VSYNCOSD_WR_MPEG_REG_BITS(
VIU_MISC_CTRL1, 0x90, 8, 8);
}
} else if (
osd_hw.osd_meson_dev.afbc_type == MALI_AFBC) {
} else if (osd_hw.osd_meson_dev.afbc_type
== MALI_AFBC) {
if (osd_hw.enable[index] == ENABLE) {
/* enable mali afbc */
VSYNCOSD_WR_MPEG_REG(
VPU_MAFBC_IRQ_MASK, 0xf);
VSYNCOSD_WR_MPEG_REG_BITS(
VPU_MAFBC_SURFACE_CFG,
1, index, 1);
@@ -3985,8 +3993,30 @@ static void osd_update_enable(u32 index)
0, index, 1);
osd_hw.osd_afbcd[index].afbc_start = 0;
}
VSYNCOSD_WR_MPEG_REG_BITS(
osd_reg->osd_ctrl_stat2, 1, 1, 1);
}
}
if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
u8 postbld_src_sel = 0;
if (osd_hw.enable[index] == ENABLE)
postbld_src_sel = (index == 0) ? 3 : 4;
if (index == 0)
VSYNCOSD_WR_MPEG_REG(OSD1_BLEND_SRC_CTRL,
(0 & 0xf) << 0 |
(0 & 0x1) << 4 |
(postbld_src_sel & 0xf) << 8 |
(0 & 0x1) << 16|
(1 & 0x1) << 20);
else if (index == 1)
VSYNCOSD_WR_MPEG_REG(OSD2_BLEND_SRC_CTRL,
(0 & 0xf) << 0 |
(0 & 0x1) << 4 |
(postbld_src_sel & 0xf) << 8 |
(0 & 0x1) << 16 |
(1 & 0x1) << 20);
}
remove_from_update_list(index, OSD_ENABLE);
}
@@ -4240,7 +4270,7 @@ static int blend_din_to_osd(
blending->osd_to_bdin_table[blend_din_index];
if ((osd_index > OSD3)
|| (osd_index < OSD1)) {
osd_log_err("blend_din:%d no match osd find!\n",
osd_log_dbg("blend_din:%d no match osd find!\n",
blend_din_index);
return -1;
} else
@@ -5082,7 +5112,7 @@ static void osd_setting_default_hwc(void)
u32 din3_osd_sel = 1;
u32 din_reoder_sel = 0x1;
u32 postbld_src3_sel = 3, postbld_src4_sel = 0;
u32 postbld_osd1_premult = 1, postbld_osd2_premult = 0;
u32 postbld_osd1_premult = 0, postbld_osd2_premult = 0;
osd_log_dbg("osd_setting_default_hwc\n");
/* depend on din0_premult_en */
@@ -5135,13 +5165,8 @@ static void osd_setting_default_hwc(void)
VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_BLEND1_SIZE,
blend_vsize << 16 |
blend_hsize);
/* close vd1, vd2 for debug */
VSYNCOSD_WR_MPEG_REG(VD1_BLEND_SRC_CTRL, 0);
VSYNCOSD_WR_MPEG_REG(VD2_BLEND_SRC_CTRL, 0);
VSYNCOSD_WR_MPEG_REG_BITS(DOLBY_PATH_CTRL,
0xf, 0, 4);
0x3, 2, 2);
}
int osd_setting_blend(void)
@@ -5171,33 +5196,29 @@ int osd_setting_blend(void)
}
void osd_mali_afbc_restart(void)
void osd_mali_afbc_start(void)
{
int i, osd_count, afbc_enable;
int i, osd_count, afbc_enable = 0;
afbc_enable = 0;
osd_count = osd_hw.osd_meson_dev.osd_count;
if ((osd_hw.osd_meson_dev.afbc_type == MALI_AFBC)
&& osd_hw.afbc_restart_in_vsync) {
VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_IRQ_MASK, 0xf);
if (osd_hw.osd_meson_dev.afbc_type == MALI_AFBC) {
for (i = 0; i < osd_count; i++) {
if (osd_hw.osd_afbcd[i].afbc_start) {
/* enable mali afbc */
VSYNCOSD_WR_MPEG_REG_BITS(
VPU_MAFBC_SURFACE_CFG,
1, i, 1);
afbc_enable = 1;
}
}
if (afbc_enable) {
if (osd_hw.afbc_use_latch)
VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_COMMAND, 0x2);
else {
osd_log_dbg("start afbc decode\n");
/* start decode */
VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_COMMAND, 1);
afbc_enable |= (1 << i);
/* afbc_enable |= 0x10000; */
}
}
/*
if (osd_hw.afbc_start_in_vsync)
VSYNCOSD_WR_MPEG_REG(
VPU_MAFBC_SURFACE_CFG,
afbc_enable);
*/
if (afbc_enable)
VSYNCOSD_WR_MPEG_REG(
VPU_MAFBC_COMMAND,
(osd_hw.afbc_use_latch ? 2 : 1));
}
}
@@ -5715,7 +5736,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
osd_hw.hw_rdma_en = 1;
} else if (osd_hw.osd_meson_dev.osd_ver == OSD_HIGH_ONE) {
osd_hw.hw_cursor_en = 0;
osd_hw.hw_rdma_en = 0;
osd_hw.hw_rdma_en = 1;
}
/* here we will init default value ,these value only set once . */
if (!logo_loaded) {
@@ -5802,10 +5823,12 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
osd_hw.premult_en[idx] = 0;
osd_hw.osd_afbcd[idx].format = COLOR_INDEX_32_ABGR;
osd_hw.osd_afbcd[idx].inter_format =
MALI_AFBC_16X16_PIXEL << 1 |
MALI_AFBC_32X8_PIXEL << 1 |
MALI_AFBC_SPLIT_ON;
osd_hw.osd_afbcd[idx].afbc_start = 0;
osd_hw.afbc_restart_in_vsync = 1;
osd_hw.afbc_start_in_vsync = 0;
osd_hw.afbc_force_reset = 1;
#if 0
/* enable for latch */
osd_hw.osd_use_latch = 1;
data32 = 0;
@@ -5814,6 +5837,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
data32 |= 0x80000000;
osd_reg_write(
hw_osd_reg_array[idx].osd_ctrl_stat, data32);
#endif
}
osd_setting_default_hwc();
}
@@ -6606,6 +6630,8 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
osd_hw.reg[OSD_ENABLE]
.update_func(index);
}
if (osd_hw.hw_rdma_en)
osd_mali_afbc_start();
osd_wait_vsync_hw();
} else if (plane_map->phy_addr && plane_map->src_w
&& plane_map->src_h && index == OSD2) {
@@ -6625,7 +6651,8 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
osd_hw.reg[OSD_ENABLE]
.update_func(index);
}
if (osd_hw.hw_rdma_en)
osd_mali_afbc_start();
}
} else {
if (plane_map->phy_addr && plane_map->src_w
@@ -6664,6 +6691,8 @@ void osd_page_flip(struct osd_plane_map_s *plane_map)
osd_hw.reg[OSD_ENABLE]
.update_func(index);
}
if (osd_hw.hw_rdma_en)
osd_mali_afbc_start();
osd_wait_vsync_hw();
}
}

2
drivers/amlogic/media/osd/osd_hw.h
View File

@@ -157,7 +157,7 @@ void osd_update_scan_mode(void);
void osd_update_3d_mode(void);
void osd_update_vsync_hit(void);
void osd_hw_reset(void);
void osd_mali_afbc_restart(void);
void osd_mali_afbc_start(void);
int logo_work_init(void);
void set_logo_loaded(void);
int set_osd_logo_freescaler(void);

8
drivers/amlogic/media/osd/osd_rdma.c
View File

@@ -921,7 +921,6 @@ static void osd_rdma_irq(void *arg)
osd_update_3d_mode();
osd_update_vsync_hit();
osd_hw_reset();
osd_mali_afbc_restart();
rdma_irq_count++;
{
/*This is a memory barrier*/
@@ -1118,7 +1117,7 @@ int osd_rdma_reset_and_flush(u32 reset_bit)
i++;
}
i = 0;
base = VPU_MAFBC_COMMAND;
base = VPU_MAFBC_IRQ_MASK;
while ((reset_bit & HW_RESET_MALI_AFBCD_REGS)
&& (i < MALI_AFBC_REG_BACKUP_COUNT)) {
addr = mali_afbc_reg_backup[i];
@@ -1128,6 +1127,11 @@ int osd_rdma_reset_and_flush(u32 reset_bit)
i++;
}
if ((reset_bit & HW_RESET_MALI_AFBCD_REGS)
&& (osd_hw.osd_meson_dev.cpu_id
== __MESON_CPU_MAJOR_ID_G12A))
wrtie_reg_internal(VPU_MAFBC_COMMAND, 1);
if (item_count < 500)
osd_reg_write(END_ADDR, (table_paddr + item_count * 8 - 1));
else {

5
drivers/amlogic/media/osd/osd_reg.h
View File

@@ -1542,10 +1542,7 @@
#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b
#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c
#define VD1_AFBCD0_MISC_CTRL 0x1a0a
#define VD2_AFBCD1_MISC_CTRL 0x1a0b
#define DOLBY_PATH_CTRL 0x1a0c
#define WR_BACK_MISC_CTRL 0x1a0d
#define DOLBY_PATH_CTRL 0x1a0c
#define OSD_PATH_MISC_CTRL 0x1a0e
#define MALI_AFBCD_TOP_CTRL 0x1a0f