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hdmitx: custombuilt: consider hdmi pll output under 1GHz

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Change-Id: I3730ad2d4c9e914c28f8d2e57da93561a72abe47
This commit is contained in:
Joy Cho
2019-01-28 15:50:39 +09:00
parent 2e6bf8fc1a
commit 64889d8edb
1 changed files with 15 additions and 5 deletions
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20
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
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@@ -1039,13 +1039,23 @@ static void hdmitx_set_clk_(struct hdmitx_dev *hdev)
next:
/* FIXME : consider pixel clocks over 200MHz */
if (vic == HDMI_CUSTOMBUILT) {
pr_info("[n2][%s] vic == HDMI_CUSTOMBUILT\n", __func__);
custom_timing = get_custom_timing();
p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10);
/* control od dividers */
p_enc[j].od1 = 1;
p_enc[j].od2 = 1;
p_enc[j].od3 = 2;
pr_info("[N2][%s] vic == HDMI_CUSTOMBUILT, frac_freq %d\n",
__func__, custom_timing->frac_freq);
/* check if hpll clk output is under (100*10)MHz */
if (p_enc[j].hpll_clk_out < 1000000) {
p_enc[j].hpll_clk_out *= 4;
/* control od dividers */
p_enc[j].od1 = 4;
p_enc[j].od2 = 1;
p_enc[j].od3 = 2;
} else {
/* control od dividers */
p_enc[j].od1 = 1;
p_enc[j].od2 = 1;
p_enc[j].od3 = 2;
}
}
hdmitx_set_cts_sys_clk(hdev);