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enable spi defconfig and rk3288 pinctrl clocks

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This commit is contained in:
luowei
2014-03-18 17:28:48 +08:00
parent db60ea3fa9
commit 6596210f6b
6 changed files with 144 additions and 21 deletions
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8
arch/arm/boot/dts/rk3188-tb.dts
View File

@@ -204,6 +204,14 @@
status = "disabled";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&i2c0 {
status = "okay";
rt5631: rt5631@1a {

82
arch/arm/boot/dts/rk3288-pinctrl.dtsi
View File

@@ -21,8 +21,8 @@
<0xff730060 0x0c>,
<0xff73006c 0x0c>;
reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 9>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates17 4>;
gpio-controller;
#gpio-cells = <2>;
@@ -34,8 +34,8 @@
gpio1: gpio1@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0xff780000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 10>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 1>;
gpio-controller;
#gpio-cells = <2>;
@@ -47,8 +47,8 @@
gpio2: gpio2@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0xff790000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 11>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 2>;
gpio-controller;
#gpio-cells = <2>;
@@ -60,8 +60,8 @@
gpio3: gpio3@ff7a0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7a0000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 12>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 3>;
gpio-controller;
#gpio-cells = <2>;
@@ -73,8 +73,8 @@
gpio4: gpio4@ff7b0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7b0000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 12>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 4>;
gpio-controller;
#gpio-cells = <2>;
@@ -86,8 +86,8 @@
gpio5: gpio5@ff7c0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7c0000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 12>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 5>;
gpio-controller;
#gpio-cells = <2>;
@@ -99,8 +99,8 @@
gpio6: gpio6@ff7d0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7d0000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 12>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 6>;
gpio-controller;
#gpio-cells = <2>;
@@ -112,8 +112,8 @@
gpio7: gpio7@ff7e0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7e0000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 12>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 7>;
gpio-controller;
#gpio-cells = <2>;
@@ -125,8 +125,8 @@
gpio8: gpio8@ff7f0000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7f0000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
//clocks = <&clk_gates8 12>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 8>;
gpio-controller;
#gpio-cells = <2>;
@@ -138,7 +138,8 @@
gpio15: gpio15@ff7f2000 {
compatible = "rockchip,gpio-bank";
reg = <0xff7f2000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates14 8>;
gpio-controller;
#gpio-cells = <2>;
@@ -505,6 +506,49 @@
};
gpio8_spi2 {
spi2_txd:spi2-txd {
rockchip,pins = <SPI2_TXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
//rockchip,voltage = <VALUE_VOL_DEFAULT>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_rxd:spi2-rxd {
rockchip,pins = <SPI2_RXD>;
rockchip,pull = <VALUE_PULL_DISABLE>;
//rockchip,voltage = <VALUE_VOL_DEFAULT>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_clk:spi2-clk {
rockchip,pins = <SPI2_CLK>;
rockchip,pull = <VALUE_PULL_DISABLE>;
//rockchip,voltage = <VALUE_VOL_DEFAULT>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_cs0:spi2-cs0 {
rockchip,pins = <SPI2_CS0>;
rockchip,pull = <VALUE_PULL_DISABLE>;
//rockchip,voltage = <VALUE_VOL_DEFAULT>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
spi2_cs1:spi2-cs1 {
rockchip,pins = <SPI2_CS1>;
rockchip,pull = <VALUE_PULL_DISABLE>;
//rockchip,voltage = <VALUE_VOL_DEFAULT>;
rockchip,drive = <VALUE_DRV_DEFAULT>;
//rockchip,tristate = <VALUE_TRI_DEFAULT>;
};
};
gpio6_i2s {
i2s_mclk:i2s-mclk {

13
arch/arm/boot/dts/rk3288-tb.dts
View File

@@ -84,6 +84,19 @@
status = "diabled";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&spi2 {
status = "okay";
};
&i2c0 {
status = "okay";
rk808: rk808@1b {

54
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -260,6 +260,60 @@
bus-width = <4>;
};
spi0: spi@ff110000 {
compatible = "rockchip,rockchip-spi";
reg = <0xff110000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
rockchip,spi-src-clk = <0>;
num-cs = <2>;
clocks =<&clk_spi0>, <&clk_gates6 4>;
clock-names = "spi","pclk_spi0";
//dmas = <&pdma1 11>, <&pdma1 12>;
//#dma-cells = <2>;
//dma-names = "tx", "rx";
status = "disabled";
};
spi1: spi@ff120000 {
compatible = "rockchip,rockchip-spi";
reg = <0xff120000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
rockchip,spi-src-clk = <1>;
num-cs = <1>;
clocks = <&clk_spi1>, <&clk_gates6 5>;
clock-names = "spi","pclk_spi1";
//dmas = <&pdma1 13>, <&pdma1 14>;
//#dma-cells = <2>;
//dma-names = "tx", "rx";
status = "disabled";
};
spi2: spi@ff130000 {
compatible = "rockchip,rockchip-spi";
reg = <0xff130000 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
rockchip,spi-src-clk = <1>;
num-cs = <2>;
clocks = <&clk_spi2>, <&clk_gates6 6>;
clock-names = "spi","pclk_spi2";
//dmas = <&pdma1 15>, <&pdma1 16>;
//#dma-cells = <2>;
//dma-names = "tx", "rx";
status = "disabled";
};
uart_dbg: serial@ff690000 {
compatible = "rockchip,serial";

4
arch/arm/configs/rockchip_defconfig
View File

@@ -302,6 +302,10 @@ CONFIG_I2C_CHARDEV=y
CONFIG_I2C_ROCKCHIP=y
CONFIG_I2C_ROCKCHIP_COMPAT=y
CONFIG_SPI=y
CONFIG_SPI_ROCKCHIP_CORE=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_ROCKCHIP_DMA=y
CONFIG_SPI_ROCKCHIP_TEST=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_THERMAL=y

4
drivers/spi/spi-rockchip-test.c
View File

@@ -46,11 +46,11 @@ static struct spi_test_data *g_spi_test_data[MAX_SPI_BUS_NUM];
static struct dw_spi_chip spi_test_chip[] = {
{
//.poll_mode = 1,
.enable_dma = 1,
//.enable_dma = 1,
},
{
//.poll_mode = 1,
.enable_dma = 1,
//.enable_dma = 1,
},
};