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clk: rockchip: rk3399: fix up the clk tree description for clk_uart4

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slove clk_uart4 set rate error.

Change-Id: Icf8f36a5c68658ed92a1b794dc68f37c729d2646
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-09-20 10:03:28 +08:00
committed by Tao Huang
parent a7e9b7ba0d
commit 6732ca7f09
2 changed files with 6 additions and 2 deletions
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7
drivers/clk/rockchip/clk-rk3399.c
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@@ -1543,8 +1543,11 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
MUX(SCLK_UART4_SRC, "clk_uart4_src", mux_24m_ppll_p, CLK_SET_RATE_NO_REPARENT,
RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS),
COMPOSITE_NOMUX(0, "clk_uart4_div", "clk_uart4_src", CLK_SET_RATE_PARENT,
RK3399_PMU_CLKSEL_CON(5), 0, 7, DFLAGS,
RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,

1
include/dt-bindings/clock/rk3399-cru.h
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@@ -370,6 +370,7 @@
#define SCLK_I2C0_PMU 9
#define SCLK_I2C4_PMU 10
#define SCLK_I2C8_PMU 11
#define SCLK_UART4_SRC 12
#define PCLK_SRC_PMU 19
#define PCLK_PMU 20