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dts: add dvalin config

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PD#156734: add dvalin gpu config

Change-Id: Ib30694b302ae9e2839cb2f64e076934c041f9ff0
Signed-off-by: Jiyu Yang <Jiyu.Yang@amlogic.com>
This commit is contained in:
Jiyu Yang
2017-12-25 14:26:45 +08:00
committed by Yixun Lan
parent c33382976f
commit 6846c23c2e
4 changed files with 135 additions and 0 deletions
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4
MAINTAINERS
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@@ -14297,3 +14297,7 @@ AMLOGIC PINCTRL DRIVER
M: Xingyu Chen <xingyu.chen@amlogic.com>
F: drivers/amlogic/pinctrl/*
F: include/dt-bindings/gpio/*
AMLOGIC GPU CONFIG
M: Jiyu Yang <Jiyu.Yang@amlogic.com>
F: arch/arm64/boot/dts/amlogic/mesong12a-dvalin.dtsi

8
arch/arm64/boot/dts/amlogic/g12a_pxp.dts
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@@ -54,6 +54,14 @@
reg = <0x0 0x05300000 0x0 0x2000000>;
no-map;
};
ion_cma_reserved:linux,ion-dev {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x8000000>;
alignment = <0x0 0x400000>;
};
};
vout {

117
arch/arm64/boot/dts/amlogic/mesong12a-dvalin.dtsi Normal file
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@@ -0,0 +1,117 @@
/*
* Amlogic G12a Platform gpu
*
* Copyright (c) 2017-2017 Amlogic Ltd
*
* This file is licensed under a dual GPLv2 or BSD license.
*
*/
/ {
dvalin@0xffe40000 {
compatible = "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
#cooling-cells = <2>; /* min followed by max */
reg = <0 0xFFE40000 0 0x04000>, /*mali APB bus base address*/
<0 0xFFD01000 0 0x01000>, /*reset register*/
<0 0xFF800000 0 0x01000>, /*aobus for gpu pmu domain*/
<0 0xFF63c000 0 0x01000>, /*hiubus for gpu clk cntl*/
<0 0xFFD01000 0 0x01000>; /*reset register*/
interrupt-parent = <&gic>;
interrupts = <0 160 4>, <0 161 4>, <0 162 4>;
interrupt-names = "GPU", "MMU", "JOB";
num_of_pp = <3>;
sc_mpp = <1>; /* number of shader cores used most of time. */
clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>;
clock-names = "gpu_mux","gp0_pll";
tbl = <&dvfs285_cfg
&dvfs400_cfg
&dvfs500_cfg
&dvfs666_cfg
&dvfs800_cfg>;
dvfs125_cfg:clk125_cfg {
clk_freq = <125000000>;
clk_parent = "fclk_div4";
clkp_freq = <500000000>;
clk_reg = <0xA03>;
voltage = <1150>;
keep_count = <5>;
threshold = <30 120>;
};
dvfs250_cfg:dvfs250_cfg {
clk_freq = <250000000>;
clk_parent = "fclk_div4";
clkp_freq = <500000000>;
clk_reg = <0xA01>;
voltage = <1150>;
keep_count = <5>;
threshold = <80 170>;
};
dvfs285_cfg:dvfs285_cfg {
clk_freq = <285714285>;
clk_parent = "fclk_div7";
clkp_freq = <285714285>;
clk_reg = <0xE00>;
voltage = <1150>;
keep_count = <5>;
threshold = <100 190>;
};
dvfs400_cfg:dvfs400_cfg {
clk_freq = <400000000>;
clk_parent = "fclk_div5";
clkp_freq = <400000000>;
clk_reg = <0xC00>;
voltage = <1150>;
keep_count = <5>;
threshold = <152 207>;
};
dvfs500_cfg:dvfs500_cfg {
clk_freq = <500000000>;
clk_parent = "fclk_div4";
clkp_freq = <500000000>;
clk_reg = <0xA00>;
voltage = <1150>;
keep_count = <5>;
threshold = <180 220>;
};
dvfs666_cfg:dvfs666_cfg {
clk_freq = <666666666>;
clk_parent = "fclk_div3";
clkp_freq = <666666666>;
clk_reg = <0x800>;
voltage = <1150>;
keep_count = <5>;
threshold = <210 236>;
};
dvfs750_cfg:dvfs750_cfg {
clk_freq = <744000000>;
clk_parent = "gp0_pll";
clkp_freq = <744000000>;
clk_reg = <0x200>;
voltage = <1150>;
keep_count = <5>;
threshold = <230 255>;
};
dvfs800_cfg:dvfs800_cfg {
clk_freq = <800000000>;
clk_parent = "gp0_pll";
clkp_freq = <800000000>;
clk_reg = <0x600>;
voltage = <1150>;
keep_count = <5>;
threshold = <230 255>;
};
};
};/* end of / */

6
arch/arm64/boot/dts/amlogic/mesong12a.dtsi
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@@ -26,6 +26,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/meson_rc.h>
#include <dt-bindings/phy/phy-amlogic-pcie.h>
#include "mesong12a-dvalin.dtsi"
/ {
cpus:cpus {
@@ -413,6 +414,11 @@
};
};/* end of hiubus*/
ion_dev {
compatible = "amlogic, ion_dev";
memory-region = <&ion_cma_reserved>;
};/* end of ion_dev*/
}; /* end of soc*/
};/* end of / */