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ASoC: rockchip: spdif: Fixed the spdif channel probability reverse issue

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Alternating playback of S16_LE and S32_LE audio
may cause the channel order to be reversed.
It need to clear MCLK domain logic before setting Fmclk/Fsdo.

Change-Id: I7cbfa01f5136b8815e5e2c6dc5dcda28ce49d13a
Signed-off-by: Zohn Ni <zohn.ni@rock-chips.com>
This commit is contained in:
Zohn Ni
2022-12-30 17:11:04 +08:00
committed by Tao Huang
parent 246e60c8a0
commit 6863df1d71
2 changed files with 8 additions and 0 deletions
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4
sound/soc/rockchip/rockchip_spdif.c
View File

@@ -170,6 +170,10 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
return -EINVAL;
}
regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLR_MASK,
SPDIF_CFGR_CLR_EN);
udelay(1);
ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
SPDIF_CFGR_CLK_DIV_MASK |
SPDIF_CFGR_HALFWORD_ENABLE |

4
sound/soc/rockchip/rockchip_spdif.h
View File

@@ -17,6 +17,10 @@
#define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
#define SPDIF_CFGR_CLK_DIV(x) ((x - 1) << SPDIF_CFGR_CLK_DIV_SHIFT)
#define SPDIF_CFGR_CLR_MASK BIT(7)
#define SPDIF_CFGR_CLR_EN BIT(7)
#define SPDIF_CFGR_CLR_DIS 0
#define SPDIF_CFGR_CSE_MASK BIT(6)
#define SPDIF_CFGR_CSE_EN BIT(6)
#define SPDIF_CFGR_CSE_DIS 0