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mmc: sdhci-of-dwcmshc: fix emmc cmd timeout issue while suspend and resume

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bug:
[  322.619045] PM: Syncing filesystems ...
[  322.669563] mmc2: error -110 doing runtime resume

Disable DLL to reset emmc sample clock and the command conflict check
function after the controller has been reset or config clock to 375Khz.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ife306fdf1c8948e7ddef4d029b850735b43865e9
This commit is contained in:
Yifeng Zhao
2021-02-21 17:44:11 +08:00
committed by Tao Huang
parent 646fea68b5
commit 69c3fdd97f
1 changed files with 9 additions and 6 deletions
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15
drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -156,8 +156,16 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
sdhci_set_clock(host, clock);
if (clock <= 400000)
/* Disable cmd conflict check */
extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
extra &= ~BIT(0);
sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
if (clock <= 400000) {
/* Disable DLL to reset sample clock */
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
return;
}
/* Reset DLL */
sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
@@ -177,11 +185,6 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
return;
}
/* Disable cmd conflict check */
extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
extra &= ~BIT(0);
sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
extra = 0x1 << 16 | /* tune clock stop en */
0x2 << 17 | /* pre-change delay */
0x3 << 19; /* post-change delay */